Start layout

This commit is contained in:
Markus Koch 2019-06-04 22:43:08 +02:00
parent a2608f41ae
commit b15d865090
3 changed files with 4048 additions and 36 deletions

View File

@ -1012,7 +1012,7 @@ F 3 "" H 2450 8150 50 0001 C CNN
1 2450 8150
1 0 0 -1
$EndComp
Text Label 1500 7250 0 50 ~ 0
Text Label 1500 7950 0 50 ~ 0
fabric_t0
Text Label 1500 7550 0 50 ~ 0
fabric_l2
@ -1164,27 +1164,27 @@ F 3 "" H 4250 6600 50 0001 C CNN
1 4250 6600
-1 0 0 -1
$EndComp
Text Label 1500 7950 0 50 ~ 0
Text Label 1500 7250 0 50 ~ 0
fabric2
Text Label 1500 9200 0 50 ~ 0
Text Label 1500 9900 0 50 ~ 0
fabric_t1
Wire Wire Line
1500 9200 1900 9200
Wire Wire Line
5200 7250 4800 7250
Text Label 5200 7250 2 50 ~ 0
Text Label 5200 7950 2 50 ~ 0
fabric_t2
Text Label 1500 9600 0 50 ~ 0
Text Label 1500 9400 0 50 ~ 0
fabric_l3
Text Label 1500 9500 0 50 ~ 0
fabric_l2
Text Label 1500 9300 0 50 ~ 0
fabric_l0
Text Label 1500 9700 0 50 ~ 0
fabric_l0
Text Label 1500 9300 0 50 ~ 0
fabric0
Text Label 1500 9800 0 50 ~ 0
Text Label 1500 9200 0 50 ~ 0
fabric1
Text Label 1500 9400 0 50 ~ 0
Text Label 1500 9600 0 50 ~ 0
fabric_l1
Wire Wire Line
1500 9900 1900 9900
@ -1200,7 +1200,7 @@ Wire Wire Line
1500 9400 1900 9400
Wire Wire Line
1500 9300 1900 9300
Text Label 1500 9900 0 50 ~ 0
Text Label 1500 9800 0 50 ~ 0
fabric2
Text Label 5200 7650 2 50 ~ 0
fabric_l3
@ -1228,19 +1228,15 @@ Wire Wire Line
5200 7450 4800 7450
Wire Wire Line
5200 7350 4800 7350
Text Label 5200 7950 2 50 ~ 0
Text Label 5200 7250 2 50 ~ 0
fabric3
Text Label 5200 9600 2 50 ~ 0
Text Label 5200 9400 2 50 ~ 0
fabric_l3
Text Label 5200 9500 2 50 ~ 0
fabric_l2
Text Label 5200 9300 2 50 ~ 0
fabric_l0
Text Label 5200 9700 2 50 ~ 0
fabric0
Text Label 5200 9800 2 50 ~ 0
fabric1
Text Label 5200 9400 2 50 ~ 0
fabric_l0
Text Label 5200 9600 2 50 ~ 0
fabric_l1
Wire Wire Line
5200 9900 4800 9900
@ -1256,11 +1252,11 @@ Wire Wire Line
5200 9400 4800 9400
Wire Wire Line
5200 9300 4800 9300
Text Label 5200 9900 2 50 ~ 0
Text Label 5200 9800 2 50 ~ 0
fabric3
Wire Wire Line
5200 9200 4800 9200
Text Label 5200 9200 2 50 ~ 0
Text Label 5200 9900 2 50 ~ 0
fabric_t3
Wire Wire Line
1900 6900 1500 6900
@ -1571,7 +1567,7 @@ Connection ~ 4050 1950
Wire Wire Line
4050 1950 4050 3150
Text Notes 1300 3850 0 50 ~ 0
ISP Configuration Bit Mapping:\n [3..0]: Route top [3..0]\n [7..4]: Route left [3..0]\n\n [9..0]: Output muxing 1&0\n [11..10]: Drive 1 / 0\n [13..12]: Output muxing 3&2\n [15..14]: Drive 3 / 2\n\n [27..16]: Input muxing\n\n [28]: Input LED enable\n [29]: Output LED _enable\n\n [30]: Synchronous mode\n [31]: LUT mode _3/4\n\n [47..32]: LUT-4 content\n [39..32]: LUT-3/A\n [47..40]: LUT-3/B
ISP Configuration Bit Mapping:\n -- OUT OF DATE --\n [3..0]: Route top [3..0]\n [7..4]: Route left [3..0]\n\n [9..0]: Output muxing 1&0\n [11..10]: Drive 1 / 0\n [13..12]: Output muxing 3&2\n [15..14]: Drive 3 / 2\n\n [27..16]: Input muxing\n\n [28]: Input LED enable\n [29]: Output LED _enable\n\n [30]: Synchronous mode\n [31]: LUT mode _3/4\n\n [47..32]: LUT-4 content\n [39..32]: LUT-3/A\n [47..40]: LUT-3/B
Wire Wire Line
1650 2100 3800 2100
Wire Wire Line
@ -2435,7 +2431,7 @@ Wire Wire Line
10250 8250 10600 8250
Wire Wire Line
9850 8250 9950 8250
Text Notes 5200 7950 0 50 ~ 0
Text Notes 5200 7250 0 50 ~ 0
*
Text Label 14350 7750 1 50 Italic 0
fabric_b3
@ -2447,10 +2443,6 @@ Text Label 13000 7750 1 50 Italic 0
fabric_b0
Text Label 14650 6050 0 50 Italic 0
fabric_r0
Wire Wire Line
14350 6050 14350 5600
Wire Wire Line
14350 7400 14350 6050
Wire Wire Line
14650 6500 13450 6500
Wire Wire Line
@ -2461,7 +2453,6 @@ Text Label 14650 6950 0 50 Italic 0
fabric_r2
Text Label 14650 7400 0 50 Italic 0
fabric_r3
Connection ~ 14350 6050
Wire Wire Line
14350 6050 14650 6050
$Sheet
@ -2501,8 +2492,14 @@ Text HLabel 13650 4350 1 50 BiDi ~ 0
fabric_t[3..0]
Text Notes 2900 9400 0 50 ~ 0
LUT Input Limitations:\n* 4-bit: Never T2+T3+F3\n T0+T1+F2\n* 3-bit: Never T2+F3, T3
Text Notes 5200 9900 0 50 ~ 0
Text Notes 5200 9800 0 50 ~ 0
*
Text Label 5200 9300 2 50 ~ 0
fabric0
Text Label 5200 9200 2 50 ~ 0
fabric1
Wire Wire Line
14350 5600 14350 7400
Wire Bus Line
13100 7850 13700 7850
Wire Bus Line

4015
kicad_pcb/ttl-fpga.kicad_pcb Normal file

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@ -581,14 +581,6 @@ F 3 "" H 3550 5400 50 0001 C CNN
1 3550 5400
1 0 0 -1
$EndComp
Wire Bus Line
6150 2600 6900 2600
Wire Bus Line
6150 5050 6900 5050
Wire Bus Line
3900 4250 3900 4550
Wire Bus Line
7450 4250 7450 4550
Wire Wire Line
4150 5350 4150 5400
$Comp
@ -602,4 +594,12 @@ F 3 "" H 4150 5400 50 0001 C CNN
1 4150 5400
1 0 0 -1
$EndComp
Wire Bus Line
7450 4250 7450 4550
Wire Bus Line
3900 4250 3900 4550
Wire Bus Line
6150 2600 6900 2600
Wire Bus Line
6150 5050 6900 5050
$EndSCHEMATC