electronics/ttl-fpga
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Redesign routing and input muxing

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This commit is contained in:
Markus Koch 2019-05-31 16:36:08 +02:00
parent 1f3df7f87c
commit d630a3ee84
4 changed files with 1828 additions and 1596 deletions
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3388
logic_block.sch
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File diff suppressed because it is too large Load Diff

2
lutd.sch
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@ -970,9 +970,9 @@ Wire Wire Line
10850 1000 10850 900
Wire Wire Line
10850 900 10650 900
Connection ~ 10650 900
Wire Bus Line
2000 2700 3850 2700
Wire Bus Line
3850 2700 3850 4950
Connection ~ 10650 900
$EndSCHEMATC

23
ttl-fpga-cache.lib
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@ -247,6 +247,29 @@ X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Q_NPN_BCE
#
DEF Device_Q_NPN_BCE Q 0 0 Y N 1 F N

11
ttl-fpga.sch
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@ -15,9 +15,18 @@ Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 4450 2100 3050 1050
S 4450 2100 2250 2250
U 5D77FDBE
F0 "LogicBlock" 50
F1 "logic_block.sch" 50
F2 "spi_mosi" I L 4450 2550 50
F3 "spi_sck" I L 4450 2450 50
F4 "spi_miso" O L 4450 2350 50
F5 "fabric_b[3..0]" I L 4450 4250 50
F6 "fabric_t[3..0]" I R 6700 2200 50
F7 "fabric_l[3..0]" I L 4450 3250 50
F8 "fabric_r[3..0]" I R 6700 3250 50
F9 "rst_n" I L 4450 3750 50
F10 "clk" I L 4450 3850 50
$EndSheet
$EndSCHEMATC