ttl-fpga/ttl-fpga.sch

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EESchema Schematic File Version 4
LIBS:ttl-fpga-cache
EELAYER 29 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 3
Title "DISCRETE TTL FPGA"
Date ""
Rev "01"
Comp "Markus Koch <markus@notsyncing.net>"
Comment1 "PCB"
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 4450 2100 2250 2250
U 5D77FDBE
F0 "LogicBlock" 50
F1 "logic_block.sch" 50
F2 "spi_mosi" I L 4450 2550 50
F3 "spi_sck" I L 4450 2450 50
F4 "spi_miso" O L 4450 2350 50
F5 "fabric_b[3..0]" I L 4450 4250 50
F6 "fabric_t[3..0]" I R 6700 2200 50
F7 "fabric_l[3..0]" I L 4450 3250 50
F8 "fabric_r[3..0]" I R 6700 3250 50
F9 "rst_n" I L 4450 3750 50
F10 "clk" I L 4450 3850 50
$EndSheet
$EndSCHEMATC