2019-05-30 20:24:33 +02:00
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EESchema Schematic File Version 4
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2019-05-30 21:12:52 +02:00
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LIBS:ttl-fpga-cache
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2019-05-30 20:24:33 +02:00
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EELAYER 29 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 3
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Title "DISCRETE TTL FPGA"
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Date ""
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Rev "01"
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Comp "Markus Koch <markus@notsyncing.net>"
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Comment1 "PCB"
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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2019-05-31 16:36:08 +02:00
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S 4450 2100 2250 2250
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2019-05-30 20:24:33 +02:00
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U 5D77FDBE
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F0 "LogicBlock" 50
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F1 "logic_block.sch" 50
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2019-05-31 16:36:08 +02:00
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F2 "spi_mosi" I L 4450 2550 50
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F3 "spi_sck" I L 4450 2450 50
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F4 "spi_miso" O L 4450 2350 50
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F5 "fabric_b[3..0]" I L 4450 4250 50
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F6 "fabric_t[3..0]" I R 6700 2200 50
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F7 "fabric_l[3..0]" I L 4450 3250 50
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F8 "fabric_r[3..0]" I R 6700 3250 50
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F9 "rst_n" I L 4450 3750 50
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F10 "clk" I L 4450 3850 50
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2019-05-30 20:24:33 +02:00
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$EndSheet
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$EndSCHEMATC
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