|
|
2c162e729b
|
Fix DRC issues
Fixes #6.
|
2019-06-01 18:31:45 +02:00 |
|
|
|
6b2fa97a6f
|
Fix right and bottom bus connections
Fixes #2.
|
2019-06-01 18:20:26 +02:00 |
|
|
|
76b1d2d01f
|
Annotate, and assign preliminary parts
|
2019-06-01 18:12:15 +02:00 |
|
|
|
037d13c5f6
|
Exchange fabric2 with fabric3 on input MUX 2
Resolves #1.
|
2019-06-01 17:51:20 +02:00 |
|
|
|
5445fa2831
|
Editorial
|
2019-05-31 22:14:42 +02:00 |
|
|
|
7066cd590e
|
Force protection resistors at fabric driver outputs
|
2019-05-31 22:12:15 +02:00 |
|
|
|
a803213b37
|
Replace mode select with schottky + negated
|
2019-05-31 21:59:05 +02:00 |
|
|
|
2a44b7d1c5
|
Replace mode select transistor logic with NOR gates
|
2019-05-31 21:06:05 +02:00 |
|
|
|
37c33e8200
|
Include LUTD config in bit map
|
2019-05-31 20:36:00 +02:00 |
|
|
|
e66cd09c68
|
Add LEDs
|
2019-05-31 18:52:59 +02:00 |
|
|
|
6cbafd76a3
|
Implement PCB top level
|
2019-05-31 18:06:53 +02:00 |
|
|
|
d630a3ee84
|
Redesign routing and input muxing
|
2019-05-31 16:36:08 +02:00 |
|
|
|
1f3df7f87c
|
Add bypass caps and clean up a bit
|
2019-05-30 21:36:22 +02:00 |
|
|
|
bf55a828a8
|
Fix LUT split enable logic
|
2019-05-30 21:12:52 +02:00 |
|
|
|
9be0ea5ed4
|
Design first draft of core logic
|
2019-05-30 20:24:33 +02:00 |
|
