kicad_clean/logic_block.sch

@@ -2447,6 +2447,10 @@ Text Label 13000 7750 1    50   Italic 0
 fabric_b0
 Text Label 14650 6050 0    50   Italic 0
 fabric_r0
+Wire Wire Line
+	14350 6050 14350 5600
+Wire Wire Line
+	14350 7400 14350 6050
 Wire Wire Line
 	14650 6500 13450 6500
 Wire Wire Line
@@ -2457,6 +2461,7 @@ Text Label 14650 6950 0    50   Italic 0
 fabric_r2
 Text Label 14650 7400 0    50   Italic 0
 fabric_r3
+Connection ~ 14350 6050
 Wire Wire Line
 	14350 6050 14650 6050
 $Sheet
@@ -2522,6 +2527,4 @@ Wire Bus Line
 	7750 1800 7750 4350
 Wire Bus Line
 	5900 1800 5900 4350
-Wire Wire Line
-	14350 5600 14350 7400
 $EndSCHEMATC

kicad_clean/ttl-fpga.sch

@@ -581,6 +581,14 @@ F 3 "" H 3550 5400 50  0001 C CNN
 	1    3550 5400
 	1    0    0    -1  
 $EndComp
+Wire Bus Line
+	6150 2600 6900 2600
+Wire Bus Line
+	6150 5050 6900 5050
+Wire Bus Line
+	3900 4250 3900 4550
+Wire Bus Line
+	7450 4250 7450 4550
 Wire Wire Line
 	4150 5350 4150 5400
 $Comp
@@ -594,12 +602,4 @@ F 3 "" H 4150 5400 50  0001 C CNN
 	1    4150 5400
 	1    0    0    -1  
 $EndComp
-Wire Bus Line
-	7450 4250 7450 4550
-Wire Bus Line
-	3900 4250 3900 4550
-Wire Bus Line
-	6150 2600 6900 2600
-Wire Bus Line
-	6150 5050 6900 5050
 $EndSCHEMATC