Compare commits
4 Commits
f60d76f831
...
0a493bdd2a
Author | SHA1 | Date | |
---|---|---|---|
0a493bdd2a | |||
a072dbfe8a | |||
a2abccfc5d | |||
7abcead6a9 |
@ -43,11 +43,9 @@ static int LUT_OUT_MUX[4][4] = {
|
|||||||
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
|
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
|
||||||
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
|
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
|
||||||
};
|
};
|
||||||
static int LUT_OUT_BITMAP[4][2] = {
|
static int LUT_OUT_BITMAP[2][2] = {
|
||||||
{27, 23},
|
{27, 23},
|
||||||
{27, 23}, /* Shared with 0 */
|
{25, 30}
|
||||||
{25, 30},
|
|
||||||
{25, 30}, /* Shared with 2 */
|
|
||||||
};
|
};
|
||||||
static int LUT_OUT_EN_N_BITMAP[4] = {
|
static int LUT_OUT_EN_N_BITMAP[4] = {
|
||||||
22, 26, 31, 24
|
22, 26, 31, 24
|
||||||
@ -76,16 +74,31 @@ static int fpga_cell_lut34_lut_get_mux(int lut, char port) {
|
|||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int fpga_cell_lut34_lut_get_out_mux(int lut, char port) {
|
static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports) {
|
||||||
int i;
|
int i;
|
||||||
|
int lut;
|
||||||
|
|
||||||
if (port == LUT_OUT_DC || port == LUT_OUT_Z)
|
ports = ports + lut_group;
|
||||||
return 255;
|
|
||||||
|
if (lut_group < 0 || lut_group > 2) {
|
||||||
|
report(LL_ERROR,
|
||||||
|
"Invalid LUT group requested.");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
lut = lut_group * 2;
|
||||||
|
|
||||||
for (i = 0; i < 4; ++i) {
|
for (i = 0; i < 4; ++i) {
|
||||||
if (LUT_OUT_MUX[lut][i] == port)
|
if (ports[0] == LUT_OUT_DC ||
|
||||||
|
ports[0] == LUT_OUT_Z ||
|
||||||
|
ports[0] == LUT_OUT_MUX[lut][i]) {
|
||||||
|
if (ports[1] == LUT_OUT_DC ||
|
||||||
|
ports[1] == LUT_OUT_Z ||
|
||||||
|
ports[1] == LUT_OUT_MUX[lut + 1][i])
|
||||||
return i;
|
return i;
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -138,13 +151,13 @@ static void fix_bitfields(int *bitmap, int count)
|
|||||||
report(LL_ERROR, errmsg, ##__VA_ARGS__);\
|
report(LL_ERROR, errmsg, ##__VA_ARGS__);\
|
||||||
errno = ERECONF;\
|
errno = ERECONF;\
|
||||||
goto fail;\
|
goto fail;\
|
||||||
}}
|
}} (void)0
|
||||||
#define BS_SET_BITS(value, nbits, mapping, errmsg, ...) \
|
#define BS_SET_BITS(value, nbits, mapping, errmsg, ...) \
|
||||||
{if (fpga_cell_bitstream_set_bits(buf, sbuf, value, nbits, mapping)) {\
|
{if (fpga_cell_bitstream_set_bits(buf, sbuf, value, nbits, mapping)) {\
|
||||||
report(LL_ERROR, errmsg, ##__VA_ARGS__);\
|
report(LL_ERROR, errmsg, ##__VA_ARGS__);\
|
||||||
errno = ERECONF;\
|
errno = ERECONF;\
|
||||||
goto fail;\
|
goto fail;\
|
||||||
}}
|
}} (void)0
|
||||||
|
|
||||||
char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
|
char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
|
||||||
{
|
{
|
||||||
@ -171,7 +184,7 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
|
|||||||
for (i = 0; i < 4; ++i) {
|
for (i = 0; i < 4; ++i) {
|
||||||
fix_bitfields(LUT_IN_BITMAP[i], 3);
|
fix_bitfields(LUT_IN_BITMAP[i], 3);
|
||||||
}
|
}
|
||||||
for (i = 0; i < 4; ++i) {
|
for (i = 0; i < 2; ++i) {
|
||||||
fix_bitfields(LUT_OUT_BITMAP[i], 2);
|
fix_bitfields(LUT_OUT_BITMAP[i], 2);
|
||||||
}
|
}
|
||||||
fix_bitfields(LUT_OUT_EN_N_BITMAP, 4);
|
fix_bitfields(LUT_OUT_EN_N_BITMAP, 4);
|
||||||
@ -205,8 +218,8 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* LUT output sel + enable */
|
/* LUT output sel + enable */
|
||||||
for (i = 0; i < 4; ++i) {
|
for (i = 0; i < 2; ++i) {
|
||||||
temp = fpga_cell_lut34_lut_get_out_mux(i, lut34->drive_sel[i]);
|
temp = fpga_cell_lut34_lut_get_out_mux(i, lut34->drive_sel);
|
||||||
|
|
||||||
if (temp < 0) {
|
if (temp < 0) {
|
||||||
report(LL_ERROR,
|
report(LL_ERROR,
|
||||||
@ -216,13 +229,11 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
|
|||||||
goto fail;
|
goto fail;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (temp != 255) {
|
|
||||||
BS_SET_BITS(temp, 2, LUT_OUT_BITMAP[i],
|
BS_SET_BITS(temp, 2, LUT_OUT_BITMAP[i],
|
||||||
"Couldn't set LUT output sel %d for output %d.", temp, i);
|
"Couldn't set LUT output sel %d for output %d.", temp, i);
|
||||||
}
|
|
||||||
|
|
||||||
}
|
}
|
||||||
for (i = 0; i < 4; ++i) {
|
for (i = 0; i < 2; ++i) {
|
||||||
temp = fpga_cell_bitstream_is_set(sbuf, LUT_OUT_BITMAP[i][0]); /* At some point, we set a specific output on this MUX */
|
temp = fpga_cell_bitstream_is_set(sbuf, LUT_OUT_BITMAP[i][0]); /* At some point, we set a specific output on this MUX */
|
||||||
BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp,
|
BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp,
|
||||||
"Couldn't %s output for output %d.",
|
"Couldn't %s output for output %d.",
|
||||||
|
@ -46,7 +46,7 @@ struct fpga_cell_lut34 {
|
|||||||
int led_lut_out_enable;
|
int led_lut_out_enable;
|
||||||
|
|
||||||
char lut_in_sel[4]; /* Input select */
|
char lut_in_sel[4]; /* Input select */
|
||||||
int drive_sel[4]; /* Which signal to drive onto each fabric line */
|
char drive_sel[4]; /* Which signal to drive onto each fabric line */
|
||||||
int sync; /* Register output on rising edge of clk */
|
int sync; /* Register output on rising edge of clk */
|
||||||
int route_en; /* Bitfield, Enable routing between {left, top} and main fabric */
|
int route_en; /* Bitfield, Enable routing between {left, top} and main fabric */
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user