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4 Commits
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0a493bdd2a
Author | SHA1 | Date | |
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0a493bdd2a | |||
a072dbfe8a | |||
a2abccfc5d | |||
7abcead6a9 |
@ -43,11 +43,9 @@ static int LUT_OUT_MUX[4][4] = {
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{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
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{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
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};
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static int LUT_OUT_BITMAP[4][2] = {
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static int LUT_OUT_BITMAP[2][2] = {
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{27, 23},
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{27, 23}, /* Shared with 0 */
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{25, 30},
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{25, 30}, /* Shared with 2 */
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{25, 30}
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};
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static int LUT_OUT_EN_N_BITMAP[4] = {
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22, 26, 31, 24
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@ -76,16 +74,31 @@ static int fpga_cell_lut34_lut_get_mux(int lut, char port) {
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return -1;
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}
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static int fpga_cell_lut34_lut_get_out_mux(int lut, char port) {
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static int fpga_cell_lut34_lut_get_out_mux(int lut_group, char *ports) {
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int i;
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int lut;
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if (port == LUT_OUT_DC || port == LUT_OUT_Z)
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return 255;
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ports = ports + lut_group;
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if (lut_group < 0 || lut_group > 2) {
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report(LL_ERROR,
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"Invalid LUT group requested.");
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return -1;
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}
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lut = lut_group * 2;
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for (i = 0; i < 4; ++i) {
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if (LUT_OUT_MUX[lut][i] == port)
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if (ports[0] == LUT_OUT_DC ||
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ports[0] == LUT_OUT_Z ||
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ports[0] == LUT_OUT_MUX[lut][i]) {
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if (ports[1] == LUT_OUT_DC ||
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ports[1] == LUT_OUT_Z ||
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ports[1] == LUT_OUT_MUX[lut + 1][i])
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return i;
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}
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}
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return -1;
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}
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@ -138,13 +151,13 @@ static void fix_bitfields(int *bitmap, int count)
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report(LL_ERROR, errmsg, ##__VA_ARGS__);\
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errno = ERECONF;\
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goto fail;\
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}}
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}} (void)0
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#define BS_SET_BITS(value, nbits, mapping, errmsg, ...) \
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{if (fpga_cell_bitstream_set_bits(buf, sbuf, value, nbits, mapping)) {\
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report(LL_ERROR, errmsg, ##__VA_ARGS__);\
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errno = ERECONF;\
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goto fail;\
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}}
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}} (void)0
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char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
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{
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@ -171,7 +184,7 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
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for (i = 0; i < 4; ++i) {
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fix_bitfields(LUT_IN_BITMAP[i], 3);
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}
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for (i = 0; i < 4; ++i) {
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for (i = 0; i < 2; ++i) {
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fix_bitfields(LUT_OUT_BITMAP[i], 2);
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}
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fix_bitfields(LUT_OUT_EN_N_BITMAP, 4);
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@ -205,8 +218,8 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
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}
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/* LUT output sel + enable */
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for (i = 0; i < 4; ++i) {
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temp = fpga_cell_lut34_lut_get_out_mux(i, lut34->drive_sel[i]);
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for (i = 0; i < 2; ++i) {
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temp = fpga_cell_lut34_lut_get_out_mux(i, lut34->drive_sel);
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if (temp < 0) {
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report(LL_ERROR,
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@ -216,13 +229,11 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
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goto fail;
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}
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if (temp != 255) {
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BS_SET_BITS(temp, 2, LUT_OUT_BITMAP[i],
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"Couldn't set LUT output sel %d for output %d.", temp, i);
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}
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}
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for (i = 0; i < 4; ++i) {
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for (i = 0; i < 2; ++i) {
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temp = fpga_cell_bitstream_is_set(sbuf, LUT_OUT_BITMAP[i][0]); /* At some point, we set a specific output on this MUX */
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BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp,
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"Couldn't %s output for output %d.",
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@ -46,7 +46,7 @@ struct fpga_cell_lut34 {
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int led_lut_out_enable;
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char lut_in_sel[4]; /* Input select */
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int drive_sel[4]; /* Which signal to drive onto each fabric line */
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char drive_sel[4]; /* Which signal to drive onto each fabric line */
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int sync; /* Register output on rising edge of clk */
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int route_en; /* Bitfield, Enable routing between {left, top} and main fabric */
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