Building an FPGA from 74-series logic ICs. For fun and education.
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Markus Koch 1f3df7f87c Add bypass caps and clean up a bit 2019-05-30 21:36:22 +02:00
.gitignore Design first draft of core logic 2019-05-30 20:24:33 +02:00
README.MD Design first draft of core logic 2019-05-30 20:24:33 +02:00
logic_block.sch Add bypass caps and clean up a bit 2019-05-30 21:36:22 +02:00
lutd.sch Add bypass caps and clean up a bit 2019-05-30 21:36:22 +02:00
sym-lib-table Fix LUT split enable logic 2019-05-30 21:12:52 +02:00
ttl-fpga-cache.lib Add bypass caps and clean up a bit 2019-05-30 21:36:22 +02:00
ttl-fpga-rescue.dcm Fix LUT split enable logic 2019-05-30 21:12:52 +02:00
ttl-fpga-rescue.lib Fix LUT split enable logic 2019-05-30 21:12:52 +02:00
ttl-fpga.pro Design first draft of core logic 2019-05-30 20:24:33 +02:00
ttl-fpga.sch Fix LUT split enable logic 2019-05-30 21:12:52 +02:00

README.MD

DISCRETE TTL FPGA

WIP.