24 lines
378 B
Plaintext
24 lines
378 B
Plaintext
EESchema Schematic File Version 4
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LIBS:ttl-fpga-cache
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EELAYER 29 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 3
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Title "DISCRETE TTL FPGA"
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Date ""
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Rev "01"
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Comp "Markus Koch <markus@notsyncing.net>"
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Comment1 "PCB"
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 4450 2100 3050 1050
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U 5D77FDBE
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F0 "LogicBlock" 50
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F1 "logic_block.sch" 50
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$EndSheet
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$EndSCHEMATC
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