.gitignore
|
Design first draft of core logic
|
2019-05-30 20:24:33 +02:00 |
logic_block.sch
|
Implement PCB top level
|
2019-05-31 18:06:53 +02:00 |
lutd.sch
|
Redesign routing and input muxing
|
2019-05-31 16:36:08 +02:00 |
README.MD
|
Design first draft of core logic
|
2019-05-30 20:24:33 +02:00 |
sym-lib-table
|
Fix LUT split enable logic
|
2019-05-30 21:12:52 +02:00 |
ttl-fpga-cache.lib
|
Implement PCB top level
|
2019-05-31 18:06:53 +02:00 |
ttl-fpga-rescue.dcm
|
Fix LUT split enable logic
|
2019-05-30 21:12:52 +02:00 |
ttl-fpga-rescue.lib
|
Fix LUT split enable logic
|
2019-05-30 21:12:52 +02:00 |
ttl-fpga.pro
|
Design first draft of core logic
|
2019-05-30 20:24:33 +02:00 |
ttl-fpga.sch
|
Implement PCB top level
|
2019-05-31 18:06:53 +02:00 |