fpga/model-ghdl
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A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.
18 Commits 2 Branches 1 Tag 86 KiB
C 95.4%
Shell 4.6%
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Makise Kurisu 2fd87d4baf Removed synopsys default for VHDL2008 support
2015-03-22 11:04:27 +01:00
vcom Removed synopsys default for VHDL2008 support 2015-03-22 11:04:27 +01:00
vsim Removed synopsys default for VHDL2008 support 2015-03-22 11:04:27 +01:00
.gitignore Fixed gitignore for build-directories 2015-01-18 21:16:02 +01:00
LICENSE Init commit 2015-01-18 20:40:39 +01:00
README.md Init commit 2015-01-18 20:40:39 +01:00

README.md

model-ghdl

A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.