140 lines
4.5 KiB
Coq
140 lines
4.5 KiB
Coq
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// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ns
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module altera_avalon_st_pipeline_base (
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clk,
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reset,
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in_ready,
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in_valid,
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in_data,
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out_ready,
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out_valid,
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out_data
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);
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parameter SYMBOLS_PER_BEAT = 1;
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parameter BITS_PER_SYMBOL = 8;
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parameter PIPELINE_READY = 1;
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localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
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input clk;
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input reset;
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output in_ready;
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input in_valid;
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input [DATA_WIDTH-1:0] in_data;
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input out_ready;
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output out_valid;
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output [DATA_WIDTH-1:0] out_data;
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reg full0;
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reg full1;
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reg [DATA_WIDTH-1:0] data0;
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reg [DATA_WIDTH-1:0] data1;
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assign out_valid = full1;
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assign out_data = data1;
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generate if (PIPELINE_READY == 1)
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begin : REGISTERED_READY_PLINE
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assign in_ready = !full0;
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always @(posedge clk, posedge reset) begin
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if (reset) begin
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data0 <= {DATA_WIDTH{1'b0}};
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data1 <= {DATA_WIDTH{1'b0}};
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end else begin
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// ----------------------------
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// always load the second slot if we can
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// ----------------------------
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if (~full0)
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data0 <= in_data;
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// ----------------------------
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// first slot is loaded either from the second,
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// or with new data
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// ----------------------------
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if (~full1 || (out_ready && out_valid)) begin
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if (full0)
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data1 <= data0;
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else
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data1 <= in_data;
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end
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end
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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full0 <= 1'b0;
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full1 <= 1'b0;
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end else begin
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// no data in pipeline
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if (~full0 & ~full1) begin
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if (in_valid) begin
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full1 <= 1'b1;
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end
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end // ~f1 & ~f0
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// one datum in pipeline
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if (full1 & ~full0) begin
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if (in_valid & ~out_ready) begin
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full0 <= 1'b1;
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end
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// back to empty
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if (~in_valid & out_ready) begin
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full1 <= 1'b0;
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end
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end // f1 & ~f0
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// two data in pipeline
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if (full1 & full0) begin
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// go back to one datum state
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if (out_ready) begin
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full0 <= 1'b0;
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end
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end // end go back to one datum stage
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end
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end
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end
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else
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begin : UNREGISTERED_READY_PLINE
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// in_ready will be a pass through of the out_ready signal as it is not registered
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assign in_ready = (~full1) | out_ready;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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data1 <= 'b0;
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full1 <= 1'b0;
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end
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else begin
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if (in_ready) begin
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data1 <= in_data;
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full1 <= in_valid;
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end
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end
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end
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end
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endgenerate
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endmodule
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