1087 lines
103 KiB
Coq
1087 lines
103 KiB
Coq
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// ddr3_0002.v
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// This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl. If you edit it your changes
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// will probably be lost.
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//
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// Generated using ACDS version 15.1 185
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`timescale 1 ps / 1 ps
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module ddr3_0002 (
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input wire pll_ref_clk, // pll_ref_clk.clk
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input wire global_reset_n, // global_reset.reset_n
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input wire soft_reset_n, // soft_reset.reset_n
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output wire afi_clk, // afi_clk.clk
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output wire afi_half_clk, // afi_half_clk.clk
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output wire afi_reset_n, // afi_reset.reset_n
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output wire afi_reset_export_n, // afi_reset_export.reset_n
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output wire [12:0] mem_a, // memory.mem_a
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output wire [2:0] mem_ba, // .mem_ba
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output wire [0:0] mem_ck, // .mem_ck
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output wire [0:0] mem_ck_n, // .mem_ck_n
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output wire [0:0] mem_cke, // .mem_cke
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output wire [0:0] mem_cs_n, // .mem_cs_n
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output wire [1:0] mem_dm, // .mem_dm
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output wire [0:0] mem_ras_n, // .mem_ras_n
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output wire [0:0] mem_cas_n, // .mem_cas_n
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output wire [0:0] mem_we_n, // .mem_we_n
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output wire mem_reset_n, // .mem_reset_n
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inout wire [15:0] mem_dq, // .mem_dq
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inout wire [1:0] mem_dqs, // .mem_dqs
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inout wire [1:0] mem_dqs_n, // .mem_dqs_n
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output wire [0:0] mem_odt, // .mem_odt
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output wire avl_ready_0, // avl_0.waitrequest_n
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input wire avl_burstbegin_0, // .beginbursttransfer
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input wire [24:0] avl_addr_0, // .address
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output wire avl_rdata_valid_0, // .readdatavalid
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output wire [31:0] avl_rdata_0, // .readdata
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input wire [31:0] avl_wdata_0, // .writedata
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input wire [3:0] avl_be_0, // .byteenable
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input wire avl_read_req_0, // .read
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input wire avl_write_req_0, // .write
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input wire [2:0] avl_size_0, // .burstcount
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input wire mp_cmd_clk_0_clk, // mp_cmd_clk_0.clk
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input wire mp_cmd_reset_n_0_reset_n, // mp_cmd_reset_n_0.reset_n
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input wire mp_rfifo_clk_0_clk, // mp_rfifo_clk_0.clk
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input wire mp_rfifo_reset_n_0_reset_n, // mp_rfifo_reset_n_0.reset_n
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input wire mp_wfifo_clk_0_clk, // mp_wfifo_clk_0.clk
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input wire mp_wfifo_reset_n_0_reset_n, // mp_wfifo_reset_n_0.reset_n
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input wire csr_clk, // csr_clk.clk
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input wire csr_reset_n, // csr_reset_n.reset_n
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output wire local_init_done, // status.local_init_done
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output wire local_cal_success, // .local_cal_success
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output wire local_cal_fail, // .local_cal_fail
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input wire oct_rzqin, // oct.rzqin
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output wire pll_mem_clk, // pll_sharing.pll_mem_clk
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output wire pll_write_clk, // .pll_write_clk
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output wire pll_locked, // .pll_locked
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output wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk
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output wire pll_addr_cmd_clk, // .pll_addr_cmd_clk
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output wire pll_avl_clk, // .pll_avl_clk
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output wire pll_config_clk, // .pll_config_clk
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output wire pll_mem_phy_clk, // .pll_mem_phy_clk
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output wire afi_phy_clk, // .afi_phy_clk
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output wire pll_avl_phy_clk // .pll_avl_phy_clk
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);
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wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
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wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
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wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
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wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
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wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
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wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
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wire p0_avl_clk_clk; // p0:avl_clk -> [dmaster:clk_clk, mm_interconnect_1:p0_avl_clk_clk, s0:avl_clk]
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wire p0_avl_reset_reset; // p0:avl_reset_n -> [dmaster:clk_reset_reset, mm_interconnect_1:dmaster_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:dmaster_master_translator_reset_reset_bridge_in_reset_reset, s0:avl_reset_n]
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wire p0_scc_clk_clk; // p0:scc_clk -> s0:scc_clk
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wire p0_scc_reset_reset; // p0:scc_reset_n -> s0:reset_n_scc_clk
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wire [15:0] s0_scc_scc_dq_ena; // s0:scc_dq_ena -> p0:scc_dq_ena
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wire [0:0] s0_scc_scc_upd; // s0:scc_upd -> p0:scc_upd
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wire [1:0] s0_scc_scc_dqs_io_ena; // s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena
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wire [1:0] s0_scc_scc_dm_ena; // s0:scc_dm_ena -> p0:scc_dm_ena
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wire [1:0] p0_scc_capture_strobe_tracking; // p0:capture_strobe_tracking -> s0:capture_strobe_tracking
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wire [1:0] s0_scc_scc_dqs_ena; // s0:scc_dqs_ena -> p0:scc_dqs_ena
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wire [0:0] s0_scc_scc_data; // s0:scc_data -> p0:scc_data
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wire [31:0] s0_avl_readdata; // p0:avl_readdata -> s0:avl_readdata
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wire s0_avl_waitrequest; // p0:avl_waitrequest -> s0:avl_waitrequest
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wire [15:0] s0_avl_address; // s0:avl_address -> p0:avl_address
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wire s0_avl_read; // s0:avl_read -> p0:avl_read
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wire s0_avl_write; // s0:avl_write -> p0:avl_write
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wire [31:0] s0_avl_writedata; // s0:avl_writedata -> p0:avl_writedata
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wire dmaster_master_reset_reset; // dmaster:master_reset_reset -> p0:csr_soft_reset_req
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wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
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wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
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wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
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wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
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wire c0_afi_afi_cal_req; // c0:afi_cal_req -> s0:afi_cal_req
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wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
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wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
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wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
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wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
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wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
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wire c0_afi_afi_init_req; // c0:afi_init_req -> s0:afi_init_req
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wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
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wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
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wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
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wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
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wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
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wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
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wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
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wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
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wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
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wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
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wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
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wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
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wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
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wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
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wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
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wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
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wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
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wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
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wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
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wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
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wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
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wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
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wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
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wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
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wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
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wire [15:0] oct0_oct_sharing_parallelterminationcontrol; // oct0:parallelterminationcontrol -> p0:parallelterminationcontrol
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wire [15:0] oct0_oct_sharing_seriesterminationcontrol; // oct0:seriesterminationcontrol -> p0:seriesterminationcontrol
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wire p0_dll_clk_clk; // p0:dll_clk -> dll0:clk
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wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll0:dll_pll_locked
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wire [6:0] dll0_dll_sharing_dll_delayctrl; // dll0:dll_delayctrl -> p0:dll_delayctrl
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wire [31:0] dmaster_master_readdata; // mm_interconnect_1:dmaster_master_readdata -> dmaster:master_readdata
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wire dmaster_master_waitrequest; // mm_interconnect_1:dmaster_master_waitrequest -> dmaster:master_waitrequest
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wire [31:0] dmaster_master_address; // dmaster:master_address -> mm_interconnect_1:dmaster_master_address
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wire dmaster_master_read; // dmaster:master_read -> mm_interconnect_1:dmaster_master_read
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wire [3:0] dmaster_master_byteenable; // dmaster:master_byteenable -> mm_interconnect_1:dmaster_master_byteenable
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wire dmaster_master_readdatavalid; // mm_interconnect_1:dmaster_master_readdatavalid -> dmaster:master_readdatavalid
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wire dmaster_master_write; // dmaster:master_write -> mm_interconnect_1:dmaster_master_write
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wire [31:0] dmaster_master_writedata; // dmaster:master_writedata -> mm_interconnect_1:dmaster_master_writedata
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wire [31:0] mm_interconnect_1_s0_seq_debug_readdata; // s0:seq_readdata -> mm_interconnect_1:s0_seq_debug_readdata
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wire mm_interconnect_1_s0_seq_debug_waitrequest; // s0:seq_waitrequest -> mm_interconnect_1:s0_seq_debug_waitrequest
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wire [31:0] mm_interconnect_1_s0_seq_debug_address; // mm_interconnect_1:s0_seq_debug_address -> s0:seq_address
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wire mm_interconnect_1_s0_seq_debug_read; // mm_interconnect_1:s0_seq_debug_read -> s0:seq_read
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wire [3:0] mm_interconnect_1_s0_seq_debug_byteenable; // mm_interconnect_1:s0_seq_debug_byteenable -> s0:seq_byteenable
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wire mm_interconnect_1_s0_seq_debug_readdatavalid; // s0:seq_readdatavalid -> mm_interconnect_1:s0_seq_debug_readdatavalid
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wire mm_interconnect_1_s0_seq_debug_write; // mm_interconnect_1:s0_seq_debug_write -> s0:seq_write
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wire [31:0] mm_interconnect_1_s0_seq_debug_writedata; // mm_interconnect_1:s0_seq_debug_writedata -> s0:seq_writedata
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wire [0:0] mm_interconnect_1_s0_seq_debug_burstcount; // mm_interconnect_1:s0_seq_debug_burstcount -> s0:seq_burstcount
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wire [31:0] if_csr_m0_master_readdata; // mm_interconnect_2:if_csr_m0_master_readdata -> if_csr_m0:master_readdata
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wire if_csr_m0_master_waitrequest; // mm_interconnect_2:if_csr_m0_master_waitrequest -> if_csr_m0:master_waitrequest
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wire [31:0] if_csr_m0_master_address; // if_csr_m0:master_address -> mm_interconnect_2:if_csr_m0_master_address
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wire if_csr_m0_master_read; // if_csr_m0:master_read -> mm_interconnect_2:if_csr_m0_master_read
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wire [3:0] if_csr_m0_master_byteenable; // if_csr_m0:master_byteenable -> mm_interconnect_2:if_csr_m0_master_byteenable
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wire if_csr_m0_master_readdatavalid; // mm_interconnect_2:if_csr_m0_master_readdatavalid -> if_csr_m0:master_readdatavalid
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wire if_csr_m0_master_write; // if_csr_m0:master_write -> mm_interconnect_2:if_csr_m0_master_write
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wire [31:0] if_csr_m0_master_writedata; // if_csr_m0:master_writedata -> mm_interconnect_2:if_csr_m0_master_writedata
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wire [31:0] mm_interconnect_2_p0_csr_readdata; // p0:csr_rdata -> mm_interconnect_2:p0_csr_readdata
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wire mm_interconnect_2_p0_csr_waitrequest; // p0:csr_waitrequest -> mm_interconnect_2:p0_csr_waitrequest
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wire [7:0] mm_interconnect_2_p0_csr_address; // mm_interconnect_2:p0_csr_address -> p0:csr_addr
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wire mm_interconnect_2_p0_csr_read; // mm_interconnect_2:p0_csr_read -> p0:csr_read_req
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wire [3:0] mm_interconnect_2_p0_csr_byteenable; // mm_interconnect_2:p0_csr_byteenable -> p0:csr_be
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wire mm_interconnect_2_p0_csr_readdatavalid; // p0:csr_rdata_valid -> mm_interconnect_2:p0_csr_readdatavalid
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wire mm_interconnect_2_p0_csr_write; // mm_interconnect_2:p0_csr_write -> p0:csr_write_req
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wire [31:0] mm_interconnect_2_p0_csr_writedata; // mm_interconnect_2:p0_csr_writedata -> p0:csr_wdata
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wire [7:0] mm_interconnect_2_c0_csr_readdata; // c0:csr_rdata -> mm_interconnect_2:c0_csr_readdata
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wire mm_interconnect_2_c0_csr_waitrequest; // c0:csr_waitrequest -> mm_interconnect_2:c0_csr_waitrequest
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wire [9:0] mm_interconnect_2_c0_csr_address; // mm_interconnect_2:c0_csr_address -> c0:csr_addr
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wire mm_interconnect_2_c0_csr_read; // mm_interconnect_2:c0_csr_read -> c0:csr_read_req
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wire [0:0] mm_interconnect_2_c0_csr_byteenable; // mm_interconnect_2:c0_csr_byteenable -> c0:csr_be
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wire mm_interconnect_2_c0_csr_readdatavalid; // c0:csr_rdata_valid -> mm_interconnect_2:c0_csr_readdatavalid
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wire mm_interconnect_2_c0_csr_write; // mm_interconnect_2:c0_csr_write -> c0:csr_write_req
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wire [7:0] mm_interconnect_2_c0_csr_writedata; // mm_interconnect_2:c0_csr_writedata -> c0:csr_wdata
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wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [c0:csr_reset_n, mm_interconnect_2:if_csr_m0_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_2:p0_csr_reset_n_reset_bridge_in_reset_reset, p0:csr_reset_n]
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ddr3_pll0 pll0 (
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.global_reset_n (global_reset_n), // global_reset.reset_n
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.afi_clk (afi_clk), // afi_clk.clk
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.afi_half_clk (afi_half_clk), // afi_half_clk.clk
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.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
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.pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
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.pll_write_clk (pll_write_clk), // .pll_write_clk
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.pll_locked (pll_locked), // .pll_locked
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.pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
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.pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk
|
||
|
|
.pll_avl_clk (pll_avl_clk), // .pll_avl_clk
|
||
|
|
.pll_config_clk (pll_config_clk), // .pll_config_clk
|
||
|
|
.pll_mem_phy_clk (pll_mem_phy_clk), // .pll_mem_phy_clk
|
||
|
|
.afi_phy_clk (afi_phy_clk), // .afi_phy_clk
|
||
|
|
.pll_avl_phy_clk (pll_avl_phy_clk) // .pll_avl_phy_clk
|
||
|
|
);
|
||
|
|
|
||
|
|
ddr3_p0 p0 (
|
||
|
|
.global_reset_n (global_reset_n), // global_reset.reset_n
|
||
|
|
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
|
||
|
|
.csr_soft_reset_req (dmaster_master_reset_reset), // csr_soft_reset_req.reset
|
||
|
|
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
|
||
|
|
.afi_reset_export_n (afi_reset_export_n), // afi_reset_export.reset_n
|
||
|
|
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
|
||
|
|
.afi_clk (afi_clk), // afi_clk.clk
|
||
|
|
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
|
||
|
|
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
|
||
|
|
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
|
||
|
|
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
|
||
|
|
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
|
||
|
|
.scc_reset_n (p0_scc_reset_reset), // scc_reset.reset_n
|
||
|
|
.avl_address (s0_avl_address), // avl.address
|
||
|
|
.avl_write (s0_avl_write), // .write
|
||
|
|
.avl_writedata (s0_avl_writedata), // .writedata
|
||
|
|
.avl_read (s0_avl_read), // .read
|
||
|
|
.avl_readdata (s0_avl_readdata), // .readdata
|
||
|
|
.avl_waitrequest (s0_avl_waitrequest), // .waitrequest
|
||
|
|
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
|
||
|
|
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
|
||
|
|
.afi_ba (c0_afi_afi_ba), // .afi_ba
|
||
|
|
.afi_cke (c0_afi_afi_cke), // .afi_cke
|
||
|
|
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
|
||
|
|
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
|
||
|
|
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
|
||
|
|
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
|
||
|
|
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
|
||
|
|
.afi_odt (c0_afi_afi_odt), // .afi_odt
|
||
|
|
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
|
||
|
|
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
|
||
|
|
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
|
||
|
|
.afi_dm (c0_afi_afi_dm), // .afi_dm
|
||
|
|
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
|
||
|
|
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
|
||
|
|
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
|
||
|
|
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
|
||
|
|
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
|
||
|
|
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
|
||
|
|
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
|
||
|
|
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
|
||
|
|
.scc_data (s0_scc_scc_data), // scc.scc_data
|
||
|
|
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
|
||
|
|
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
|
||
|
|
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
|
||
|
|
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
|
||
|
|
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
|
||
|
|
.scc_upd (s0_scc_scc_upd), // .scc_upd
|
||
|
|
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
|
||
|
|
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
|
||
|
|
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
|
||
|
|
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
|
||
|
|
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
|
||
|
|
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
|
||
|
|
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
|
||
|
|
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
|
||
|
|
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
|
||
|
|
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
|
||
|
|
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
|
||
|
|
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
|
||
|
|
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
|
||
|
|
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
|
||
|
|
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
|
||
|
|
.pll_mem_clk (pll_mem_clk), // pll_sharing.pll_mem_clk
|
||
|
|
.pll_write_clk (pll_write_clk), // .pll_write_clk
|
||
|
|
.pll_locked (pll_locked), // .pll_locked
|
||
|
|
.pll_write_clk_pre_phy_clk (pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
|
||
|
|
.pll_addr_cmd_clk (pll_addr_cmd_clk), // .pll_addr_cmd_clk
|
||
|
|
.pll_avl_clk (pll_avl_clk), // .pll_avl_clk
|
||
|
|
.pll_config_clk (pll_config_clk), // .pll_config_clk
|
||
|
|
.pll_mem_phy_clk (pll_mem_phy_clk), // .pll_mem_phy_clk
|
||
|
|
.afi_phy_clk (afi_phy_clk), // .afi_phy_clk
|
||
|
|
.pll_avl_phy_clk (pll_avl_phy_clk), // .pll_avl_phy_clk
|
||
|
|
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
|
||
|
|
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl), // .dll_delayctrl
|
||
|
|
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
|
||
|
|
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
|
||
|
|
.mem_a (mem_a), // memory.mem_a
|
||
|
|
.mem_ba (mem_ba), // .mem_ba
|
||
|
|
.mem_ck (mem_ck), // .mem_ck
|
||
|
|
.mem_ck_n (mem_ck_n), // .mem_ck_n
|
||
|
|
.mem_cke (mem_cke), // .mem_cke
|
||
|
|
.mem_cs_n (mem_cs_n), // .mem_cs_n
|
||
|
|
.mem_dm (mem_dm), // .mem_dm
|
||
|
|
.mem_ras_n (mem_ras_n), // .mem_ras_n
|
||
|
|
.mem_cas_n (mem_cas_n), // .mem_cas_n
|
||
|
|
.mem_we_n (mem_we_n), // .mem_we_n
|
||
|
|
.mem_reset_n (mem_reset_n), // .mem_reset_n
|
||
|
|
.mem_dq (mem_dq), // .mem_dq
|
||
|
|
.mem_dqs (mem_dqs), // .mem_dqs
|
||
|
|
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
|
||
|
|
.mem_odt (mem_odt), // .mem_odt
|
||
|
|
.csr_clk (csr_clk), // csr_clk.clk
|
||
|
|
.csr_reset_n (~rst_controller_reset_out_reset), // csr_reset_n.reset_n
|
||
|
|
.csr_write_req (mm_interconnect_2_p0_csr_write), // csr.write
|
||
|
|
.csr_read_req (mm_interconnect_2_p0_csr_read), // .read
|
||
|
|
.csr_waitrequest (mm_interconnect_2_p0_csr_waitrequest), // .waitrequest
|
||
|
|
.csr_addr (mm_interconnect_2_p0_csr_address), // .address
|
||
|
|
.csr_be (mm_interconnect_2_p0_csr_byteenable), // .byteenable
|
||
|
|
.csr_wdata (mm_interconnect_2_p0_csr_writedata), // .writedata
|
||
|
|
.csr_rdata (mm_interconnect_2_p0_csr_readdata), // .readdata
|
||
|
|
.csr_rdata_valid (mm_interconnect_2_p0_csr_readdatavalid), // .readdatavalid
|
||
|
|
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
|
||
|
|
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
|
||
|
|
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
|
||
|
|
.io_intbadout (12'b000000000000), // (terminated)
|
||
|
|
.io_intcasndout (4'b0000), // (terminated)
|
||
|
|
.io_intckdout (4'b0000), // (terminated)
|
||
|
|
.io_intckedout (8'b00000000), // (terminated)
|
||
|
|
.io_intckndout (4'b0000), // (terminated)
|
||
|
|
.io_intcsndout (8'b00000000), // (terminated)
|
||
|
|
.io_intdmdout (20'b00000000000000000000), // (terminated)
|
||
|
|
.io_intdqdin (), // (terminated)
|
||
|
|
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
|
||
|
|
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
|
||
|
|
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
|
||
|
|
.io_intdqsboe (10'b0000000000), // (terminated)
|
||
|
|
.io_intdqsdout (20'b00000000000000000000), // (terminated)
|
||
|
|
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
|
||
|
|
.io_intdqslogicfiforeset (5'b00000), // (terminated)
|
||
|
|
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
|
||
|
|
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
|
||
|
|
.io_intdqslogicoct (10'b0000000000), // (terminated)
|
||
|
|
.io_intdqslogicrdatavalid (), // (terminated)
|
||
|
|
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
|
||
|
|
.io_intdqsoe (10'b0000000000), // (terminated)
|
||
|
|
.io_intodtdout (8'b00000000), // (terminated)
|
||
|
|
.io_intrasndout (4'b0000), // (terminated)
|
||
|
|
.io_intresetndout (4'b0000), // (terminated)
|
||
|
|
.io_intwendout (4'b0000), // (terminated)
|
||
|
|
.io_intafirlat (), // (terminated)
|
||
|
|
.io_intafiwlat () // (terminated)
|
||
|
|
);
|
||
|
|
|
||
|
|
ddr3_s0 s0 (
|
||
|
|
.avl_clk (p0_avl_clk_clk), // avl_clk.clk
|
||
|
|
.avl_reset_n (p0_avl_reset_reset), // avl_reset.reset_n
|
||
|
|
.scc_clk (p0_scc_clk_clk), // scc_clk.clk
|
||
|
|
.reset_n_scc_clk (p0_scc_reset_reset), // scc_reset.reset_n
|
||
|
|
.scc_data (s0_scc_scc_data), // scc.scc_data
|
||
|
|
.scc_dqs_ena (s0_scc_scc_dqs_ena), // .scc_dqs_ena
|
||
|
|
.scc_dqs_io_ena (s0_scc_scc_dqs_io_ena), // .scc_dqs_io_ena
|
||
|
|
.scc_dq_ena (s0_scc_scc_dq_ena), // .scc_dq_ena
|
||
|
|
.scc_dm_ena (s0_scc_scc_dm_ena), // .scc_dm_ena
|
||
|
|
.capture_strobe_tracking (p0_scc_capture_strobe_tracking), // .capture_strobe_tracking
|
||
|
|
.scc_upd (s0_scc_scc_upd), // .scc_upd
|
||
|
|
.afi_init_req (c0_afi_afi_init_req), // afi_init_cal_req.afi_init_req
|
||
|
|
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
|
||
|
|
.avl_address (s0_avl_address), // avl.address
|
||
|
|
.avl_write (s0_avl_write), // .write
|
||
|
|
.avl_writedata (s0_avl_writedata), // .writedata
|
||
|
|
.avl_read (s0_avl_read), // .read
|
||
|
|
.avl_readdata (s0_avl_readdata), // .readdata
|
||
|
|
.avl_waitrequest (s0_avl_waitrequest), // .waitrequest
|
||
|
|
.seq_waitrequest (mm_interconnect_1_s0_seq_debug_waitrequest), // seq_debug.waitrequest
|
||
|
|
.seq_readdata (mm_interconnect_1_s0_seq_debug_readdata), // .readdata
|
||
|
|
.seq_readdatavalid (mm_interconnect_1_s0_seq_debug_readdatavalid), // .readdatavalid
|
||
|
|
.seq_burstcount (mm_interconnect_1_s0_seq_debug_burstcount), // .burstcount
|
||
|
|
.seq_writedata (mm_interconnect_1_s0_seq_debug_writedata), // .writedata
|
||
|
|
.seq_address (mm_interconnect_1_s0_seq_debug_address), // .address
|
||
|
|
.seq_write (mm_interconnect_1_s0_seq_debug_write), // .write
|
||
|
|
.seq_read (mm_interconnect_1_s0_seq_debug_read), // .read
|
||
|
|
.seq_byteenable (mm_interconnect_1_s0_seq_debug_byteenable), // .byteenable
|
||
|
|
.seq_debugaccess (1'b0) // (terminated)
|
||
|
|
);
|
||
|
|
|
||
|
|
ddr3_dmaster #(
|
||
|
|
.USE_PLI (0),
|
||
|
|
.PLI_PORT (50000),
|
||
|
|
.FIFO_DEPTHS (2)
|
||
|
|
) dmaster (
|
||
|
|
.clk_clk (p0_avl_clk_clk), // clk.clk
|
||
|
|
.clk_reset_reset (~p0_avl_reset_reset), // clk_reset.reset
|
||
|
|
.master_address (dmaster_master_address), // master.address
|
||
|
|
.master_readdata (dmaster_master_readdata), // .readdata
|
||
|
|
.master_read (dmaster_master_read), // .read
|
||
|
|
.master_write (dmaster_master_write), // .write
|
||
|
|
.master_writedata (dmaster_master_writedata), // .writedata
|
||
|
|
.master_waitrequest (dmaster_master_waitrequest), // .waitrequest
|
||
|
|
.master_readdatavalid (dmaster_master_readdatavalid), // .readdatavalid
|
||
|
|
.master_byteenable (dmaster_master_byteenable), // .byteenable
|
||
|
|
.master_reset_reset (dmaster_master_reset_reset) // master_reset.reset
|
||
|
|
);
|
||
|
|
|
||
|
|
altera_mem_if_hard_memory_controller_top_cyclonev #(
|
||
|
|
.MEM_IF_DQS_WIDTH (2),
|
||
|
|
.MEM_IF_CS_WIDTH (1),
|
||
|
|
.MEM_IF_CHIP_BITS (1),
|
||
|
|
.MEM_IF_CLK_PAIR_COUNT (1),
|
||
|
|
.CSR_ADDR_WIDTH (10),
|
||
|
|
.CSR_DATA_WIDTH (8),
|
||
|
|
.CSR_BE_WIDTH (1),
|
||
|
|
.AVL_ADDR_WIDTH (25),
|
||
|
|
.AVL_DATA_WIDTH (32),
|
||
|
|
.AVL_SIZE_WIDTH (3),
|
||
|
|
.AVL_DATA_WIDTH_PORT_0 (32),
|
||
|
|
.AVL_ADDR_WIDTH_PORT_0 (25),
|
||
|
|
.AVL_NUM_SYMBOLS_PORT_0 (4),
|
||
|
|
.LSB_WFIFO_PORT_0 (0),
|
||
|
|
.MSB_WFIFO_PORT_0 (0),
|
||
|
|
.LSB_RFIFO_PORT_0 (0),
|
||
|
|
.MSB_RFIFO_PORT_0 (0),
|
||
|
|
.AVL_DATA_WIDTH_PORT_1 (1),
|
||
|
|
.AVL_ADDR_WIDTH_PORT_1 (1),
|
||
|
|
.AVL_NUM_SYMBOLS_PORT_1 (1),
|
||
|
|
.LSB_WFIFO_PORT_1 (5),
|
||
|
|
.MSB_WFIFO_PORT_1 (5),
|
||
|
|
.LSB_RFIFO_PORT_1 (5),
|
||
|
|
.MSB_RFIFO_PORT_1 (5),
|
||
|
|
.AVL_DATA_WIDTH_PORT_2 (1),
|
||
|
|
.AVL_ADDR_WIDTH_PORT_2 (1),
|
||
|
|
.AVL_NUM_SYMBOLS_PORT_2 (1),
|
||
|
|
.LSB_WFIFO_PORT_2 (5),
|
||
|
|
.MSB_WFIFO_PORT_2 (5),
|
||
|
|
.LSB_RFIFO_PORT_2 (5),
|
||
|
|
.MSB_RFIFO_PORT_2 (5),
|
||
|
|
.AVL_DATA_WIDTH_PORT_3 (1),
|
||
|
|
.AVL_ADDR_WIDTH_PORT_3 (1),
|
||
|
|
.AVL_NUM_SYMBOLS_PORT_3 (1),
|
||
|
|
.LSB_WFIFO_PORT_3 (5),
|
||
|
|
.MSB_WFIFO_PORT_3 (5),
|
||
|
|
.LSB_RFIFO_PORT_3 (5),
|
||
|
|
.MSB_RFIFO_PORT_3 (5),
|
||
|
|
.AVL_DATA_WIDTH_PORT_4 (1),
|
||
|
|
.AVL_ADDR_WIDTH_PORT_4 (1),
|
||
|
|
.AVL_NUM_SYMBOLS_PORT_4 (1),
|
||
|
|
.LSB_WFIFO_PORT_4 (5),
|
||
|
|
.MSB_WFIFO_PORT_4 (5),
|
||
|
|
.LSB_RFIFO_PORT_4 (5),
|
||
|
|
.MSB_RFIFO_PORT_4 (5),
|
||
|
|
.AVL_DATA_WIDTH_PORT_5 (1),
|
||
|
|
.AVL_ADDR_WIDTH_PORT_5 (1),
|
||
|
|
.AVL_NUM_SYMBOLS_PORT_5 (1),
|
||
|
|
.LSB_WFIFO_PORT_5 (5),
|
||
|
|
.MSB_WFIFO_PORT_5 (5),
|
||
|
|
.LSB_RFIFO_PORT_5 (5),
|
||
|
|
.MSB_RFIFO_PORT_5 (5),
|
||
|
|
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
|
||
|
|
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
|
||
|
|
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
|
||
|
|
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
|
||
|
|
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
|
||
|
|
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
|
||
|
|
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
|
||
|
|
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
|
||
|
|
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
|
||
|
|
.ENUM_CAL_REQ ("DISABLED"),
|
||
|
|
.ENUM_CFG_BURST_LENGTH ("BL_8"),
|
||
|
|
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_16"),
|
||
|
|
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
|
||
|
|
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_4"),
|
||
|
|
.ENUM_CFG_TYPE ("DDR3"),
|
||
|
|
.ENUM_CLOCK_OFF_0 ("DISABLED"),
|
||
|
|
.ENUM_CLOCK_OFF_1 ("DISABLED"),
|
||
|
|
.ENUM_CLOCK_OFF_2 ("DISABLED"),
|
||
|
|
.ENUM_CLOCK_OFF_3 ("DISABLED"),
|
||
|
|
.ENUM_CLOCK_OFF_4 ("DISABLED"),
|
||
|
|
.ENUM_CLOCK_OFF_5 ("DISABLED"),
|
||
|
|
.ENUM_CLR_INTR ("NO_CLR_INTR"),
|
||
|
|
.ENUM_CMD_PORT_IN_USE_0 ("TRUE"),
|
||
|
|
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
|
||
|
|
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
|
||
|
|
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
|
||
|
|
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
|
||
|
|
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
|
||
|
|
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT0_TYPE ("BI_DIRECTION"),
|
||
|
|
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT1_TYPE ("DISABLE"),
|
||
|
|
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT2_TYPE ("DISABLE"),
|
||
|
|
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT3_TYPE ("DISABLE"),
|
||
|
|
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT4_TYPE ("DISABLE"),
|
||
|
|
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CPORT5_TYPE ("DISABLE"),
|
||
|
|
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
|
||
|
|
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
|
||
|
|
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
|
||
|
|
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
|
||
|
|
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
|
||
|
|
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
|
||
|
|
.ENUM_CTRL_WIDTH ("DATA_WIDTH_32_BIT"),
|
||
|
|
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
|
||
|
|
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
|
||
|
|
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
|
||
|
|
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
|
||
|
|
.ENUM_ENABLE_ATPG ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_DQS_TRACKING ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_INTR ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_NO_DM ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
|
||
|
|
.ENUM_GANGED_ARF ("DISABLED"),
|
||
|
|
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
|
||
|
|
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
|
||
|
|
.ENUM_INC_SYNC ("FIFO_SET_2"),
|
||
|
|
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
|
||
|
|
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
|
||
|
|
.ENUM_MASK_DBE_INTR ("DISABLED"),
|
||
|
|
.ENUM_MASK_SBE_INTR ("DISABLED"),
|
||
|
|
.ENUM_MEM_IF_AL ("AL_0"),
|
||
|
|
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
|
||
|
|
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
|
||
|
|
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
|
||
|
|
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
|
||
|
|
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
|
||
|
|
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
|
||
|
|
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_2"),
|
||
|
|
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_16"),
|
||
|
|
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
|
||
|
|
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_13"),
|
||
|
|
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
|
||
|
|
.ENUM_MEM_IF_TCCD ("TCCD_4"),
|
||
|
|
.ENUM_MEM_IF_TCL ("TCL_7"),
|
||
|
|
.ENUM_MEM_IF_TCWL ("TCWL_6"),
|
||
|
|
.ENUM_MEM_IF_TFAW ("TFAW_14"),
|
||
|
|
.ENUM_MEM_IF_TMRD ("TMRD_4"),
|
||
|
|
.ENUM_MEM_IF_TRAS ("TRAS_11"),
|
||
|
|
.ENUM_MEM_IF_TRC ("TRC_15"),
|
||
|
|
.ENUM_MEM_IF_TRCD ("TRCD_5"),
|
||
|
|
.ENUM_MEM_IF_TRP ("TRP_5"),
|
||
|
|
.ENUM_MEM_IF_TRRD ("TRRD_3"),
|
||
|
|
.ENUM_MEM_IF_TRTP ("TRTP_3"),
|
||
|
|
.ENUM_MEM_IF_TWR ("TWR_5"),
|
||
|
|
.ENUM_MEM_IF_TWTR ("TWTR_5"),
|
||
|
|
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
|
||
|
|
.ENUM_OUTPUT_REGD ("DISABLED"),
|
||
|
|
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
|
||
|
|
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
|
||
|
|
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
|
||
|
|
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
|
||
|
|
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
|
||
|
|
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
|
||
|
|
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
|
||
|
|
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
|
||
|
|
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
|
||
|
|
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
|
||
|
|
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
|
||
|
|
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
|
||
|
|
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
|
||
|
|
.ENUM_RD_DWIDTH_0 ("DWIDTH_32"),
|
||
|
|
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
|
||
|
|
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
|
||
|
|
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
|
||
|
|
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
|
||
|
|
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
|
||
|
|
.ENUM_RD_FIFO_IN_USE_0 ("TRUE"),
|
||
|
|
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
|
||
|
|
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
|
||
|
|
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
|
||
|
|
.ENUM_RD_PORT_INFO_0 ("USE_0"),
|
||
|
|
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
|
||
|
|
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
|
||
|
|
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
|
||
|
|
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
|
||
|
|
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
|
||
|
|
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
|
||
|
|
.ENUM_REORDER_DATA ("NO_DATA_REORDERING"),
|
||
|
|
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
|
||
|
|
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
|
||
|
|
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
|
||
|
|
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
|
||
|
|
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
|
||
|
|
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
|
||
|
|
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
|
||
|
|
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
|
||
|
|
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
|
||
|
|
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
|
||
|
|
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
|
||
|
|
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
|
||
|
|
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
|
||
|
|
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
|
||
|
|
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
|
||
|
|
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
|
||
|
|
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
|
||
|
|
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
|
||
|
|
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
|
||
|
|
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
|
||
|
|
.ENUM_TEST_MODE ("NORMAL_MODE"),
|
||
|
|
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
|
||
|
|
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
|
||
|
|
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
|
||
|
|
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
|
||
|
|
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
|
||
|
|
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
|
||
|
|
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
|
||
|
|
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
|
||
|
|
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
|
||
|
|
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
|
||
|
|
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
|
||
|
|
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
|
||
|
|
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
|
||
|
|
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
|
||
|
|
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
|
||
|
|
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
|
||
|
|
.ENUM_USER_ECC_EN ("DISABLE"),
|
||
|
|
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
|
||
|
|
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
|
||
|
|
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
|
||
|
|
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
|
||
|
|
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
|
||
|
|
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
|
||
|
|
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
|
||
|
|
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
|
||
|
|
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
|
||
|
|
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
|
||
|
|
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
|
||
|
|
.ENUM_WR_DWIDTH_0 ("DWIDTH_32"),
|
||
|
|
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
|
||
|
|
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
|
||
|
|
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
|
||
|
|
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
|
||
|
|
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
|
||
|
|
.ENUM_WR_FIFO_IN_USE_0 ("TRUE"),
|
||
|
|
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
|
||
|
|
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
|
||
|
|
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
|
||
|
|
.ENUM_WR_PORT_INFO_0 ("USE_0"),
|
||
|
|
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
|
||
|
|
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
|
||
|
|
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
|
||
|
|
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
|
||
|
|
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
|
||
|
|
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
|
||
|
|
.INTG_MEM_AUTO_PD_CYCLES (0),
|
||
|
|
.INTG_CYC_TO_RLD_JARS_0 (1),
|
||
|
|
.INTG_CYC_TO_RLD_JARS_1 (1),
|
||
|
|
.INTG_CYC_TO_RLD_JARS_2 (1),
|
||
|
|
.INTG_CYC_TO_RLD_JARS_3 (1),
|
||
|
|
.INTG_CYC_TO_RLD_JARS_4 (1),
|
||
|
|
.INTG_CYC_TO_RLD_JARS_5 (1),
|
||
|
|
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
|
||
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
|
||
|
|
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
|
||
|
|
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
|
||
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
|
||
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
|
||
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
|
||
|
|
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
|
||
|
|
.INTG_MEM_IF_TREFI (2341),
|
||
|
|
.INTG_MEM_IF_TRFC (34),
|
||
|
|
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
|
||
|
|
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
|
||
|
|
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
|
||
|
|
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
|
||
|
|
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
|
||
|
|
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
|
||
|
|
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
|
||
|
|
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
|
||
|
|
.INTG_SUM_WT_PRIORITY_0 (0),
|
||
|
|
.INTG_SUM_WT_PRIORITY_1 (0),
|
||
|
|
.INTG_SUM_WT_PRIORITY_2 (0),
|
||
|
|
.INTG_SUM_WT_PRIORITY_3 (0),
|
||
|
|
.INTG_SUM_WT_PRIORITY_4 (0),
|
||
|
|
.INTG_SUM_WT_PRIORITY_5 (0),
|
||
|
|
.INTG_SUM_WT_PRIORITY_6 (0),
|
||
|
|
.INTG_SUM_WT_PRIORITY_7 (0),
|
||
|
|
.INTG_POWER_SAVING_EXIT_CYCLES (5),
|
||
|
|
.INTG_MEM_CLK_ENTRY_CYCLES (10),
|
||
|
|
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
|
||
|
|
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
|
||
|
|
.AFI_RATE_RATIO (1),
|
||
|
|
.AFI_ADDR_WIDTH (13),
|
||
|
|
.AFI_BANKADDR_WIDTH (3),
|
||
|
|
.AFI_CONTROL_WIDTH (1),
|
||
|
|
.AFI_CS_WIDTH (1),
|
||
|
|
.AFI_DM_WIDTH (4),
|
||
|
|
.AFI_DQ_WIDTH (32),
|
||
|
|
.AFI_ODT_WIDTH (1),
|
||
|
|
.AFI_WRITE_DQS_WIDTH (2),
|
||
|
|
.AFI_RLAT_WIDTH (6),
|
||
|
|
.AFI_WLAT_WIDTH (6),
|
||
|
|
.HARD_PHY (1)
|
||
|
|
) c0 (
|
||
|
|
.afi_clk (afi_clk), // afi_clk.clk
|
||
|
|
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
|
||
|
|
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
|
||
|
|
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
|
||
|
|
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
|
||
|
|
.mp_cmd_clk_0 (mp_cmd_clk_0_clk), // mp_cmd_clk_0.clk
|
||
|
|
.mp_cmd_reset_n_0 (mp_cmd_reset_n_0_reset_n), // mp_cmd_reset_n_0.reset_n
|
||
|
|
.mp_rfifo_clk_0 (mp_rfifo_clk_0_clk), // mp_rfifo_clk_0.clk
|
||
|
|
.mp_rfifo_reset_n_0 (mp_rfifo_reset_n_0_reset_n), // mp_rfifo_reset_n_0.reset_n
|
||
|
|
.mp_wfifo_clk_0 (mp_wfifo_clk_0_clk), // mp_wfifo_clk_0.clk
|
||
|
|
.mp_wfifo_reset_n_0 (mp_wfifo_reset_n_0_reset_n), // mp_wfifo_reset_n_0.reset_n
|
||
|
|
.csr_clk (csr_clk), // csr_clk.clk
|
||
|
|
.csr_reset_n (~rst_controller_reset_out_reset), // csr_reset_n.reset_n
|
||
|
|
.avl_ready_0 (avl_ready_0), // avl_0.waitrequest_n
|
||
|
|
.avl_burstbegin_0 (avl_burstbegin_0), // .beginbursttransfer
|
||
|
|
.avl_addr_0 (avl_addr_0), // .address
|
||
|
|
.avl_rdata_valid_0 (avl_rdata_valid_0), // .readdatavalid
|
||
|
|
.avl_rdata_0 (avl_rdata_0), // .readdata
|
||
|
|
.avl_wdata_0 (avl_wdata_0), // .writedata
|
||
|
|
.avl_be_0 (avl_be_0), // .byteenable
|
||
|
|
.avl_read_req_0 (avl_read_req_0), // .read
|
||
|
|
.avl_write_req_0 (avl_write_req_0), // .write
|
||
|
|
.avl_size_0 (avl_size_0), // .burstcount
|
||
|
|
.local_init_done (local_init_done), // status.local_init_done
|
||
|
|
.local_cal_success (local_cal_success), // .local_cal_success
|
||
|
|
.local_cal_fail (local_cal_fail), // .local_cal_fail
|
||
|
|
.csr_write_req (mm_interconnect_2_c0_csr_write), // csr.write
|
||
|
|
.csr_read_req (mm_interconnect_2_c0_csr_read), // .read
|
||
|
|
.csr_waitrequest (mm_interconnect_2_c0_csr_waitrequest), // .waitrequest
|
||
|
|
.csr_addr (mm_interconnect_2_c0_csr_address), // .address
|
||
|
|
.csr_be (mm_interconnect_2_c0_csr_byteenable), // .byteenable
|
||
|
|
.csr_wdata (mm_interconnect_2_c0_csr_writedata), // .writedata
|
||
|
|
.csr_rdata (mm_interconnect_2_c0_csr_readdata), // .readdata
|
||
|
|
.csr_rdata_valid (mm_interconnect_2_c0_csr_readdatavalid), // .readdatavalid
|
||
|
|
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
|
||
|
|
.afi_ba (c0_afi_afi_ba), // .afi_ba
|
||
|
|
.afi_cke (c0_afi_afi_cke), // .afi_cke
|
||
|
|
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
|
||
|
|
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
|
||
|
|
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
|
||
|
|
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
|
||
|
|
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
|
||
|
|
.afi_odt (c0_afi_afi_odt), // .afi_odt
|
||
|
|
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
|
||
|
|
.afi_init_req (c0_afi_afi_init_req), // .afi_init_req
|
||
|
|
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
|
||
|
|
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
|
||
|
|
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
|
||
|
|
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
|
||
|
|
.afi_dm (c0_afi_afi_dm), // .afi_dm
|
||
|
|
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
|
||
|
|
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
|
||
|
|
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
|
||
|
|
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
|
||
|
|
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
|
||
|
|
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
|
||
|
|
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
|
||
|
|
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
|
||
|
|
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
|
||
|
|
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
|
||
|
|
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
|
||
|
|
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
|
||
|
|
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
|
||
|
|
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
|
||
|
|
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
|
||
|
|
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
|
||
|
|
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
|
||
|
|
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
|
||
|
|
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
|
||
|
|
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
|
||
|
|
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
|
||
|
|
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
|
||
|
|
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
|
||
|
|
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
|
||
|
|
.mp_cmd_clk_1 (1'b0), // (terminated)
|
||
|
|
.mp_cmd_reset_n_1 (1'b1), // (terminated)
|
||
|
|
.mp_cmd_clk_2 (1'b0), // (terminated)
|
||
|
|
.mp_cmd_reset_n_2 (1'b1), // (terminated)
|
||
|
|
.mp_cmd_clk_3 (1'b0), // (terminated)
|
||
|
|
.mp_cmd_reset_n_3 (1'b1), // (terminated)
|
||
|
|
.mp_cmd_clk_4 (1'b0), // (terminated)
|
||
|
|
.mp_cmd_reset_n_4 (1'b1), // (terminated)
|
||
|
|
.mp_cmd_clk_5 (1'b0), // (terminated)
|
||
|
|
.mp_cmd_reset_n_5 (1'b1), // (terminated)
|
||
|
|
.mp_rfifo_clk_1 (1'b0), // (terminated)
|
||
|
|
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
|
||
|
|
.mp_wfifo_clk_1 (1'b0), // (terminated)
|
||
|
|
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
|
||
|
|
.mp_rfifo_clk_2 (1'b0), // (terminated)
|
||
|
|
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
|
||
|
|
.mp_wfifo_clk_2 (1'b0), // (terminated)
|
||
|
|
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
|
||
|
|
.mp_rfifo_clk_3 (1'b0), // (terminated)
|
||
|
|
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
|
||
|
|
.mp_wfifo_clk_3 (1'b0), // (terminated)
|
||
|
|
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
|
||
|
|
.avl_ready_1 (), // (terminated)
|
||
|
|
.avl_burstbegin_1 (1'b0), // (terminated)
|
||
|
|
.avl_addr_1 (1'b0), // (terminated)
|
||
|
|
.avl_rdata_valid_1 (), // (terminated)
|
||
|
|
.avl_rdata_1 (), // (terminated)
|
||
|
|
.avl_wdata_1 (1'b0), // (terminated)
|
||
|
|
.avl_be_1 (1'b0), // (terminated)
|
||
|
|
.avl_read_req_1 (1'b0), // (terminated)
|
||
|
|
.avl_write_req_1 (1'b0), // (terminated)
|
||
|
|
.avl_size_1 (3'b000), // (terminated)
|
||
|
|
.avl_ready_2 (), // (terminated)
|
||
|
|
.avl_burstbegin_2 (1'b0), // (terminated)
|
||
|
|
.avl_addr_2 (1'b0), // (terminated)
|
||
|
|
.avl_rdata_valid_2 (), // (terminated)
|
||
|
|
.avl_rdata_2 (), // (terminated)
|
||
|
|
.avl_wdata_2 (1'b0), // (terminated)
|
||
|
|
.avl_be_2 (1'b0), // (terminated)
|
||
|
|
.avl_read_req_2 (1'b0), // (terminated)
|
||
|
|
.avl_write_req_2 (1'b0), // (terminated)
|
||
|
|
.avl_size_2 (3'b000), // (terminated)
|
||
|
|
.avl_ready_3 (), // (terminated)
|
||
|
|
.avl_burstbegin_3 (1'b0), // (terminated)
|
||
|
|
.avl_addr_3 (1'b0), // (terminated)
|
||
|
|
.avl_rdata_valid_3 (), // (terminated)
|
||
|
|
.avl_rdata_3 (), // (terminated)
|
||
|
|
.avl_wdata_3 (1'b0), // (terminated)
|
||
|
|
.avl_be_3 (1'b0), // (terminated)
|
||
|
|
.avl_read_req_3 (1'b0), // (terminated)
|
||
|
|
.avl_write_req_3 (1'b0), // (terminated)
|
||
|
|
.avl_size_3 (3'b000), // (terminated)
|
||
|
|
.avl_ready_4 (), // (terminated)
|
||
|
|
.avl_burstbegin_4 (1'b0), // (terminated)
|
||
|
|
.avl_addr_4 (1'b0), // (terminated)
|
||
|
|
.avl_rdata_valid_4 (), // (terminated)
|
||
|
|
.avl_rdata_4 (), // (terminated)
|
||
|
|
.avl_wdata_4 (1'b0), // (terminated)
|
||
|
|
.avl_be_4 (1'b0), // (terminated)
|
||
|
|
.avl_read_req_4 (1'b0), // (terminated)
|
||
|
|
.avl_write_req_4 (1'b0), // (terminated)
|
||
|
|
.avl_size_4 (3'b000), // (terminated)
|
||
|
|
.avl_ready_5 (), // (terminated)
|
||
|
|
.avl_burstbegin_5 (1'b0), // (terminated)
|
||
|
|
.avl_addr_5 (1'b0), // (terminated)
|
||
|
|
.avl_rdata_valid_5 (), // (terminated)
|
||
|
|
.avl_rdata_5 (), // (terminated)
|
||
|
|
.avl_wdata_5 (1'b0), // (terminated)
|
||
|
|
.avl_be_5 (1'b0), // (terminated)
|
||
|
|
.avl_read_req_5 (1'b0), // (terminated)
|
||
|
|
.avl_write_req_5 (1'b0), // (terminated)
|
||
|
|
.avl_size_5 (3'b000), // (terminated)
|
||
|
|
.afi_seq_busy (1'b0), // (terminated)
|
||
|
|
.afi_ctl_refresh_done (), // (terminated)
|
||
|
|
.afi_ctl_long_idle (), // (terminated)
|
||
|
|
.local_multicast (1'b0), // (terminated)
|
||
|
|
.local_refresh_req (1'b0), // (terminated)
|
||
|
|
.local_refresh_chip (1'b0), // (terminated)
|
||
|
|
.local_refresh_ack (), // (terminated)
|
||
|
|
.local_self_rfsh_req (1'b0), // (terminated)
|
||
|
|
.local_self_rfsh_chip (1'b0), // (terminated)
|
||
|
|
.local_self_rfsh_ack (), // (terminated)
|
||
|
|
.local_deep_powerdn_req (1'b0), // (terminated)
|
||
|
|
.local_deep_powerdn_chip (1'b0), // (terminated)
|
||
|
|
.local_deep_powerdn_ack (), // (terminated)
|
||
|
|
.local_powerdn_ack (), // (terminated)
|
||
|
|
.local_priority (1'b0), // (terminated)
|
||
|
|
.bonding_in_1 (4'b0000), // (terminated)
|
||
|
|
.bonding_in_2 (6'b000000), // (terminated)
|
||
|
|
.bonding_in_3 (6'b000000), // (terminated)
|
||
|
|
.bonding_out_1 (), // (terminated)
|
||
|
|
.bonding_out_2 (), // (terminated)
|
||
|
|
.bonding_out_3 () // (terminated)
|
||
|
|
);
|
||
|
|
|
||
|
|
altera_mem_if_oct_cyclonev #(
|
||
|
|
.OCT_TERM_CONTROL_WIDTH (16)
|
||
|
|
) oct0 (
|
||
|
|
.oct_rzqin (oct_rzqin), // oct.rzqin
|
||
|
|
.seriesterminationcontrol (oct0_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
|
||
|
|
.parallelterminationcontrol (oct0_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
|
||
|
|
);
|
||
|
|
|
||
|
|
altera_mem_if_dll_cyclonev #(
|
||
|
|
.DLL_DELAY_CTRL_WIDTH (7),
|
||
|
|
.DLL_OFFSET_CTRL_WIDTH (6),
|
||
|
|
.DELAY_BUFFER_MODE ("HIGH"),
|
||
|
|
.DELAY_CHAIN_LENGTH (8),
|
||
|
|
.DLL_INPUT_FREQUENCY_PS_STR ("3333 ps")
|
||
|
|
) dll0 (
|
||
|
|
.clk (p0_dll_clk_clk), // clk.clk
|
||
|
|
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
|
||
|
|
.dll_delayctrl (dll0_dll_sharing_dll_delayctrl) // .dll_delayctrl
|
||
|
|
);
|
||
|
|
|
||
|
|
ddr3_dmaster #(
|
||
|
|
.USE_PLI (0),
|
||
|
|
.PLI_PORT (50000),
|
||
|
|
.FIFO_DEPTHS (2)
|
||
|
|
) if_csr_m0 (
|
||
|
|
.clk_clk (csr_clk), // clk.clk
|
||
|
|
.clk_reset_reset (~csr_reset_n), // clk_reset.reset
|
||
|
|
.master_address (if_csr_m0_master_address), // master.address
|
||
|
|
.master_readdata (if_csr_m0_master_readdata), // .readdata
|
||
|
|
.master_read (if_csr_m0_master_read), // .read
|
||
|
|
.master_write (if_csr_m0_master_write), // .write
|
||
|
|
.master_writedata (if_csr_m0_master_writedata), // .writedata
|
||
|
|
.master_waitrequest (if_csr_m0_master_waitrequest), // .waitrequest
|
||
|
|
.master_readdatavalid (if_csr_m0_master_readdatavalid), // .readdatavalid
|
||
|
|
.master_byteenable (if_csr_m0_master_byteenable), // .byteenable
|
||
|
|
.master_reset_reset () // master_reset.reset
|
||
|
|
);
|
||
|
|
|
||
|
|
ddr3_mm_interconnect_1 mm_interconnect_1 (
|
||
|
|
.p0_avl_clk_clk (p0_avl_clk_clk), // p0_avl_clk.clk
|
||
|
|
.dmaster_clk_reset_reset_bridge_in_reset_reset (~p0_avl_reset_reset), // dmaster_clk_reset_reset_bridge_in_reset.reset
|
||
|
|
.dmaster_master_translator_reset_reset_bridge_in_reset_reset (~p0_avl_reset_reset), // dmaster_master_translator_reset_reset_bridge_in_reset.reset
|
||
|
|
.dmaster_master_address (dmaster_master_address), // dmaster_master.address
|
||
|
|
.dmaster_master_waitrequest (dmaster_master_waitrequest), // .waitrequest
|
||
|
|
.dmaster_master_byteenable (dmaster_master_byteenable), // .byteenable
|
||
|
|
.dmaster_master_read (dmaster_master_read), // .read
|
||
|
|
.dmaster_master_readdata (dmaster_master_readdata), // .readdata
|
||
|
|
.dmaster_master_readdatavalid (dmaster_master_readdatavalid), // .readdatavalid
|
||
|
|
.dmaster_master_write (dmaster_master_write), // .write
|
||
|
|
.dmaster_master_writedata (dmaster_master_writedata), // .writedata
|
||
|
|
.s0_seq_debug_address (mm_interconnect_1_s0_seq_debug_address), // s0_seq_debug.address
|
||
|
|
.s0_seq_debug_write (mm_interconnect_1_s0_seq_debug_write), // .write
|
||
|
|
.s0_seq_debug_read (mm_interconnect_1_s0_seq_debug_read), // .read
|
||
|
|
.s0_seq_debug_readdata (mm_interconnect_1_s0_seq_debug_readdata), // .readdata
|
||
|
|
.s0_seq_debug_writedata (mm_interconnect_1_s0_seq_debug_writedata), // .writedata
|
||
|
|
.s0_seq_debug_burstcount (mm_interconnect_1_s0_seq_debug_burstcount), // .burstcount
|
||
|
|
.s0_seq_debug_byteenable (mm_interconnect_1_s0_seq_debug_byteenable), // .byteenable
|
||
|
|
.s0_seq_debug_readdatavalid (mm_interconnect_1_s0_seq_debug_readdatavalid), // .readdatavalid
|
||
|
|
.s0_seq_debug_waitrequest (mm_interconnect_1_s0_seq_debug_waitrequest) // .waitrequest
|
||
|
|
);
|
||
|
|
|
||
|
|
ddr3_mm_interconnect_2 mm_interconnect_2 (
|
||
|
|
.csr_clk_out_clk_clk (csr_clk), // csr_clk_out_clk.clk
|
||
|
|
.if_csr_m0_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // if_csr_m0_clk_reset_reset_bridge_in_reset.reset
|
||
|
|
.p0_csr_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // p0_csr_reset_n_reset_bridge_in_reset.reset
|
||
|
|
.if_csr_m0_master_address (if_csr_m0_master_address), // if_csr_m0_master.address
|
||
|
|
.if_csr_m0_master_waitrequest (if_csr_m0_master_waitrequest), // .waitrequest
|
||
|
|
.if_csr_m0_master_byteenable (if_csr_m0_master_byteenable), // .byteenable
|
||
|
|
.if_csr_m0_master_read (if_csr_m0_master_read), // .read
|
||
|
|
.if_csr_m0_master_readdata (if_csr_m0_master_readdata), // .readdata
|
||
|
|
.if_csr_m0_master_readdatavalid (if_csr_m0_master_readdatavalid), // .readdatavalid
|
||
|
|
.if_csr_m0_master_write (if_csr_m0_master_write), // .write
|
||
|
|
.if_csr_m0_master_writedata (if_csr_m0_master_writedata), // .writedata
|
||
|
|
.c0_csr_address (mm_interconnect_2_c0_csr_address), // c0_csr.address
|
||
|
|
.c0_csr_write (mm_interconnect_2_c0_csr_write), // .write
|
||
|
|
.c0_csr_read (mm_interconnect_2_c0_csr_read), // .read
|
||
|
|
.c0_csr_readdata (mm_interconnect_2_c0_csr_readdata), // .readdata
|
||
|
|
.c0_csr_writedata (mm_interconnect_2_c0_csr_writedata), // .writedata
|
||
|
|
.c0_csr_byteenable (mm_interconnect_2_c0_csr_byteenable), // .byteenable
|
||
|
|
.c0_csr_readdatavalid (mm_interconnect_2_c0_csr_readdatavalid), // .readdatavalid
|
||
|
|
.c0_csr_waitrequest (mm_interconnect_2_c0_csr_waitrequest), // .waitrequest
|
||
|
|
.p0_csr_address (mm_interconnect_2_p0_csr_address), // p0_csr.address
|
||
|
|
.p0_csr_write (mm_interconnect_2_p0_csr_write), // .write
|
||
|
|
.p0_csr_read (mm_interconnect_2_p0_csr_read), // .read
|
||
|
|
.p0_csr_readdata (mm_interconnect_2_p0_csr_readdata), // .readdata
|
||
|
|
.p0_csr_writedata (mm_interconnect_2_p0_csr_writedata), // .writedata
|
||
|
|
.p0_csr_byteenable (mm_interconnect_2_p0_csr_byteenable), // .byteenable
|
||
|
|
.p0_csr_readdatavalid (mm_interconnect_2_p0_csr_readdatavalid), // .readdatavalid
|
||
|
|
.p0_csr_waitrequest (mm_interconnect_2_p0_csr_waitrequest) // .waitrequest
|
||
|
|
);
|
||
|
|
|
||
|
|
altera_reset_controller #(
|
||
|
|
.NUM_RESET_INPUTS (1),
|
||
|
|
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
||
|
|
.SYNC_DEPTH (2),
|
||
|
|
.RESET_REQUEST_PRESENT (0),
|
||
|
|
.RESET_REQ_WAIT_TIME (1),
|
||
|
|
.MIN_RST_ASSERTION_TIME (3),
|
||
|
|
.RESET_REQ_EARLY_DSRT_TIME (1),
|
||
|
|
.USE_RESET_REQUEST_IN0 (0),
|
||
|
|
.USE_RESET_REQUEST_IN1 (0),
|
||
|
|
.USE_RESET_REQUEST_IN2 (0),
|
||
|
|
.USE_RESET_REQUEST_IN3 (0),
|
||
|
|
.USE_RESET_REQUEST_IN4 (0),
|
||
|
|
.USE_RESET_REQUEST_IN5 (0),
|
||
|
|
.USE_RESET_REQUEST_IN6 (0),
|
||
|
|
.USE_RESET_REQUEST_IN7 (0),
|
||
|
|
.USE_RESET_REQUEST_IN8 (0),
|
||
|
|
.USE_RESET_REQUEST_IN9 (0),
|
||
|
|
.USE_RESET_REQUEST_IN10 (0),
|
||
|
|
.USE_RESET_REQUEST_IN11 (0),
|
||
|
|
.USE_RESET_REQUEST_IN12 (0),
|
||
|
|
.USE_RESET_REQUEST_IN13 (0),
|
||
|
|
.USE_RESET_REQUEST_IN14 (0),
|
||
|
|
.USE_RESET_REQUEST_IN15 (0),
|
||
|
|
.ADAPT_RESET_REQUEST (0)
|
||
|
|
) rst_controller (
|
||
|
|
.reset_in0 (~csr_reset_n), // reset_in0.reset
|
||
|
|
.clk (csr_clk), // clk.clk
|
||
|
|
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
|
||
|
|
.reset_req (), // (terminated)
|
||
|
|
.reset_req_in0 (1'b0), // (terminated)
|
||
|
|
.reset_in1 (1'b0), // (terminated)
|
||
|
|
.reset_req_in1 (1'b0), // (terminated)
|
||
|
|
.reset_in2 (1'b0), // (terminated)
|
||
|
|
.reset_req_in2 (1'b0), // (terminated)
|
||
|
|
.reset_in3 (1'b0), // (terminated)
|
||
|
|
.reset_req_in3 (1'b0), // (terminated)
|
||
|
|
.reset_in4 (1'b0), // (terminated)
|
||
|
|
.reset_req_in4 (1'b0), // (terminated)
|
||
|
|
.reset_in5 (1'b0), // (terminated)
|
||
|
|
.reset_req_in5 (1'b0), // (terminated)
|
||
|
|
.reset_in6 (1'b0), // (terminated)
|
||
|
|
.reset_req_in6 (1'b0), // (terminated)
|
||
|
|
.reset_in7 (1'b0), // (terminated)
|
||
|
|
.reset_req_in7 (1'b0), // (terminated)
|
||
|
|
.reset_in8 (1'b0), // (terminated)
|
||
|
|
.reset_req_in8 (1'b0), // (terminated)
|
||
|
|
.reset_in9 (1'b0), // (terminated)
|
||
|
|
.reset_req_in9 (1'b0), // (terminated)
|
||
|
|
.reset_in10 (1'b0), // (terminated)
|
||
|
|
.reset_req_in10 (1'b0), // (terminated)
|
||
|
|
.reset_in11 (1'b0), // (terminated)
|
||
|
|
.reset_req_in11 (1'b0), // (terminated)
|
||
|
|
.reset_in12 (1'b0), // (terminated)
|
||
|
|
.reset_req_in12 (1'b0), // (terminated)
|
||
|
|
.reset_in13 (1'b0), // (terminated)
|
||
|
|
.reset_req_in13 (1'b0), // (terminated)
|
||
|
|
.reset_in14 (1'b0), // (terminated)
|
||
|
|
.reset_req_in14 (1'b0), // (terminated)
|
||
|
|
.reset_in15 (1'b0), // (terminated)
|
||
|
|
.reset_req_in15 (1'b0) // (terminated)
|
||
|
|
);
|
||
|
|
|
||
|
|
endmodule
|