196 lines
6.7 KiB
Coq
196 lines
6.7 KiB
Coq
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// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1 ps / 1 ps
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module ddr3_p0_altdqdqs (
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core_clock_in,
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reset_n_core_clock_in,
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fr_clock_in,
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hr_clock_in,
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write_strobe_clock_in,
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write_strobe,
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strobe_ena_hr_clock_in,
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read_write_data_io,
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write_oe_in,
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strobe_io,
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output_strobe_ena,
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strobe_n_io,
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oct_ena_in,
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read_data_out,
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capture_strobe_out,
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write_data_in,
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extra_write_data_in,
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extra_write_data_out,
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parallelterminationcontrol_in,
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seriesterminationcontrol_in,
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config_data_in,
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config_update,
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config_dqs_ena,
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config_io_ena,
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config_extra_io_ena,
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config_dqs_io_ena,
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config_clock_in,
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lfifo_rdata_en,
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lfifo_rdata_en_full,
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lfifo_rd_latency,
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lfifo_reset_n,
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lfifo_rdata_valid,
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vfifo_qvld,
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vfifo_inc_wr_ptr,
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vfifo_reset_n,
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rfifo_reset_n,
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dll_delayctrl_in
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);
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input [7-1:0] dll_delayctrl_in;
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input core_clock_in;
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input reset_n_core_clock_in;
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input fr_clock_in;
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input hr_clock_in;
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input write_strobe_clock_in;
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input [3:0] write_strobe;
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input strobe_ena_hr_clock_in;
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inout [8-1:0] read_write_data_io;
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input [2*8-1:0] write_oe_in;
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inout strobe_io;
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input [2-1:0] output_strobe_ena;
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inout strobe_n_io;
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input [2-1:0] oct_ena_in;
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output [2 * 2 * 8-1:0] read_data_out;
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output capture_strobe_out;
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input [2 * 2 * 8-1:0] write_data_in;
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input [2 * 2 * 1-1:0] extra_write_data_in;
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output [1-1:0] extra_write_data_out;
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input [16-1:0] parallelterminationcontrol_in;
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input [16-1:0] seriesterminationcontrol_in;
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input config_data_in;
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input config_update;
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input config_dqs_ena;
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input [8-1:0] config_io_ena;
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input [1-1:0] config_extra_io_ena;
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input config_dqs_io_ena;
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input config_clock_in;
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input [2-1:0] lfifo_rdata_en;
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input [2-1:0] lfifo_rdata_en_full;
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input [4:0] lfifo_rd_latency;
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input lfifo_reset_n;
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output lfifo_rdata_valid;
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input [2-1:0] vfifo_qvld;
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input [2-1:0] vfifo_inc_wr_ptr;
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input vfifo_reset_n;
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input rfifo_reset_n;
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parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
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altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
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.core_clock_in( core_clock_in),
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.reset_n_core_clock_in (reset_n_core_clock_in),
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.fr_clock_in( fr_clock_in),
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.hr_clock_in( hr_clock_in),
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.write_strobe_clock_in (write_strobe_clock_in),
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.write_strobe(write_strobe),
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.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
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.read_write_data_io( read_write_data_io),
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.write_oe_in( write_oe_in),
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.strobe_io( strobe_io),
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.output_strobe_ena( output_strobe_ena),
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.strobe_n_io( strobe_n_io),
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.oct_ena_in( oct_ena_in),
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.read_data_out( read_data_out),
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.capture_strobe_out( capture_strobe_out),
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.write_data_in( write_data_in),
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.extra_write_data_in( extra_write_data_in),
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.extra_write_data_out( extra_write_data_out),
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.parallelterminationcontrol_in( parallelterminationcontrol_in),
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.seriesterminationcontrol_in( seriesterminationcontrol_in),
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.config_data_in( config_data_in),
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.config_update( config_update),
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.config_dqs_ena( config_dqs_ena),
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.config_io_ena( config_io_ena),
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.config_extra_io_ena( config_extra_io_ena),
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.config_dqs_io_ena( config_dqs_io_ena),
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.config_clock_in( config_clock_in),
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.lfifo_rdata_en(lfifo_rdata_en),
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.lfifo_rdata_en_full(lfifo_rdata_en_full),
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.lfifo_rd_latency(lfifo_rd_latency),
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.lfifo_reset_n(lfifo_reset_n),
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.lfifo_rdata_valid(lfifo_rdata_valid),
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.vfifo_qvld(vfifo_qvld),
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.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
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.vfifo_reset_n(vfifo_reset_n),
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.rfifo_reset_n(rfifo_reset_n),
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.dll_delayctrl_in(dll_delayctrl_in)
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);
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defparam altdq_dqs2_inst.PIN_WIDTH = 8;
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defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
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defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
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defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
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defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
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defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
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defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
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defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
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defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
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defparam altdq_dqs2_inst.INPUT_FREQ = 300.0;
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defparam altdq_dqs2_inst.INPUT_FREQ_PS = "3333 ps";
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defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
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defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
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defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
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defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
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defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
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defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
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defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
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defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
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defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
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defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
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defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
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defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
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defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
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defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
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defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
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defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
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defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
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defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
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defparam altdq_dqs2_inst.DLL_WIDTH = 7;
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defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
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defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
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defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
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defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
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defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
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defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false";
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defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
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defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
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defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
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defparam altdq_dqs2_inst.USE_2X_FF = "false";
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defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
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defparam altdq_dqs2_inst.USE_DQS_TRACKING = "false";
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defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
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defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
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defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
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defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
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defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
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defparam altdq_dqs2_inst.HHP_HPS = "false";
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endmodule
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