106 lines
3.8 KiB
Tcl
106 lines
3.8 KiB
Tcl
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#
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# AUTO-GENERATED FILE: Do not edit ! ! !
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#
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set ::GLOBAL_ddr3_p0_corename "ddr3_p0"
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set ::GLOBAL_ddr3_p0_io_standard "SSTL-15"
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set ::GLOBAL_ddr3_p0_io_interface_type "HPAD"
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set ::GLOBAL_ddr3_p0_io_standard_differential "1.5-V SSTL"
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set ::GLOBAL_ddr3_p0_io_standard_cmos "1.5V"
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set ::GLOBAL_ddr3_p0_number_of_dqs_groups 2
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set ::GLOBAL_ddr3_p0_dqs_group_size 8
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set ::GLOBAL_ddr3_p0_number_of_ck_pins 1
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set ::GLOBAL_ddr3_p0_number_of_dm_pins 2
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set ::GLOBAL_ddr3_p0_dqs_delay_chain_length 0
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set ::GLOBAL_ddr3_p0_uniphy_temp_ver_code 1003457432
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# PLL Parameters
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#USER W A R N I N G !
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#USER The PLL parameters are statically defined in this
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#USER file at generation time!
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#USER To ensure timing constraints and timing reports are correct, when you make
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#USER any changes to the PLL component using the MegaWizard Plug-In,
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#USER apply those changes to the PLL parameters in this file
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set ::GLOBAL_ddr3_p0_num_pll_clock 7
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set ::GLOBAL_ddr3_p0_pll_mult(0) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(0) 1000000
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set ::GLOBAL_ddr3_p0_pll_phase(0) 0.0
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set ::GLOBAL_ddr3_p0_pll_mult(PLL_AFI_CLK) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(PLL_AFI_CLK) 1000000
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set ::GLOBAL_ddr3_p0_pll_phase(PLL_AFI_CLK) 0.0
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set ::GLOBAL_ddr3_p0_pll_mult(1) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(1) 1000000
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set ::GLOBAL_ddr3_p0_pll_phase(1) 0.0
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set ::GLOBAL_ddr3_p0_pll_mult(PLL_MEM_CLK) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(PLL_MEM_CLK) 1000000
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set ::GLOBAL_ddr3_p0_pll_phase(PLL_MEM_CLK) 0.0
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set ::GLOBAL_ddr3_p0_pll_mult(2) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(2) 1000000
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set ::GLOBAL_ddr3_p0_pll_phase(2) 270.0
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set ::GLOBAL_ddr3_p0_pll_mult(PLL_WRITE_CLK) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(PLL_WRITE_CLK) 1000000
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set ::GLOBAL_ddr3_p0_pll_phase(PLL_WRITE_CLK) 270.0
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set ::GLOBAL_ddr3_p0_pll_mult(3) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(3) 1000000
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set ::GLOBAL_ddr3_p0_pll_phase(3) 270.0
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set ::GLOBAL_ddr3_p0_pll_mult(PLL_ADDR_CMD_CLK) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(PLL_ADDR_CMD_CLK) 1000000
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set ::GLOBAL_ddr3_p0_pll_phase(PLL_ADDR_CMD_CLK) 270.0
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set ::GLOBAL_ddr3_p0_pll_mult(4) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(4) 2000000
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set ::GLOBAL_ddr3_p0_pll_phase(4) 0.0
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set ::GLOBAL_ddr3_p0_pll_mult(PLL_AFI_HALF_CLK) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(PLL_AFI_HALF_CLK) 2000000
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set ::GLOBAL_ddr3_p0_pll_phase(PLL_AFI_HALF_CLK) 0.0
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set ::GLOBAL_ddr3_p0_pll_mult(5) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(5) 5000000
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set ::GLOBAL_ddr3_p0_pll_phase(5) 9.0
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set ::GLOBAL_ddr3_p0_pll_mult(PLL_NIOS_CLK) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(PLL_NIOS_CLK) 5000000
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set ::GLOBAL_ddr3_p0_pll_phase(PLL_NIOS_CLK) 9.0
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set ::GLOBAL_ddr3_p0_pll_mult(6) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(6) 15000000
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set ::GLOBAL_ddr3_p0_pll_phase(6) 0.0
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set ::GLOBAL_ddr3_p0_pll_mult(PLL_CONFIG_CLK) 6000000
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set ::GLOBAL_ddr3_p0_pll_div(PLL_CONFIG_CLK) 15000000
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set ::GLOBAL_ddr3_p0_pll_phase(PLL_CONFIG_CLK) 0.0
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set ::GLOBAL_ddr3_p0_leveling_capture_phase 90.0
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##############################################################
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## IP options
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##############################################################
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set IP(write_dcc) "static"
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set IP(write_deskew_range) 31
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set IP(read_deskew_range) 31
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set IP(write_deskew_range_setup) 4
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set IP(write_deskew_range_hold) 31
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set IP(read_deskew_range_setup) 31
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set IP(read_deskew_range_hold) 31
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set IP(mem_if_memtype) "ddr3"
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set IP(RDIMM) 0
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set IP(LRDIMM) 0
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set IP(mp_calibration) 1
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set IP(quantization_T9) 0.025
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set IP(quantization_T1) 0.025
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set IP(quantization_DCC) 0.025
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set IP(quantization_T7) 0.025
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set IP(quantization_WL) 0.0125
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set IP(quantization_T11) 0.025
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set IP(eol_reduction_factor_addr) 2.0
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set IP(eol_reduction_factor_read) 2.1
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set IP(eol_reduction_factor_write) 2.35
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# Can be either dynamic or static
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set IP(write_deskew_mode) "dynamic"
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set IP(read_deskew_mode) "dynamic"
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set IP(discrete_device) 0
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set IP(num_ranks) 1
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set IP(num_shadow_registers) 1
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set IP(tracking_enabled) 0
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set IP(num_report_paths) 10
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set IP(epr) 0.058
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set IP(epw) 0.076
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