226 lines
8.5 KiB
Plaintext
226 lines
8.5 KiB
Plaintext
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--IP Functional Simulation Model
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--VERSION_BEGIN 15.1 cbx_mgl 2015:10:21:19:02:34:SJ cbx_simgen 2015:10:14:18:59:15:SJ VERSION_END
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-- Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, the Altera Quartus Prime License Agreement,
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-- the Altera MegaCore Function License Agreement, or other
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-- applicable license agreement, including, without limitation,
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-- that your use is for the sole purpose of programming logic
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-- devices manufactured by Altera and sold by Altera or its
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-- authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-- You may only use these simulation model output files for simulation
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-- purposes and expressly not for synthesis or any other purposes (in which
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-- event Altera disclaims all warranties of any kind).
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--synopsys translate_off
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LIBRARY altera_lnsim;
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USE altera_lnsim.altera_lnsim_components.all;
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--synthesis_resources = generic_pll 9
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY ddr3_pll0 IS
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PORT
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(
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afi_clk : OUT STD_LOGIC;
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afi_half_clk : OUT STD_LOGIC;
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afi_phy_clk : OUT STD_LOGIC;
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global_reset_n : IN STD_LOGIC;
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pll_addr_cmd_clk : OUT STD_LOGIC;
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pll_avl_clk : OUT STD_LOGIC;
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pll_avl_phy_clk : OUT STD_LOGIC;
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pll_config_clk : OUT STD_LOGIC;
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pll_locked : OUT STD_LOGIC;
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pll_mem_clk : OUT STD_LOGIC;
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pll_mem_phy_clk : OUT STD_LOGIC;
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pll_ref_clk : IN STD_LOGIC;
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pll_write_clk : OUT STD_LOGIC;
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pll_write_clk_pre_phy_clk : OUT STD_LOGIC
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);
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END ddr3_pll0;
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ARCHITECTURE RTL OF ddr3_pll0 IS
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ATTRIBUTE synthesis_clearbox : natural;
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ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
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SIGNAL wire_ddr3_pll0_generic_pll_pll1_56_fboutclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll1_56_locked : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll1_56_outclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll1_56_rst : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll1_phy_58_outclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll1_phy_58_rst : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll2_60_outclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll2_60_rst : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll2_phy_62_outclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll2_phy_62_rst : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll3_64_outclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll3_64_rst : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll4_66_outclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll4_66_rst : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll6_68_outclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll6_68_rst : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll6_phy_70_outclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll6_phy_70_rst : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll7_72_outclk : STD_LOGIC;
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SIGNAL wire_ddr3_pll0_generic_pll_pll7_72_rst : STD_LOGIC;
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SIGNAL wire_w_lg_global_reset_n1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
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BEGIN
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wire_w_lg_global_reset_n1w(0) <= NOT global_reset_n;
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afi_clk <= wire_ddr3_pll0_generic_pll_pll1_56_outclk;
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afi_half_clk <= '0';
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afi_phy_clk <= wire_ddr3_pll0_generic_pll_pll1_phy_58_outclk;
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pll_addr_cmd_clk <= wire_ddr3_pll0_generic_pll_pll4_66_outclk;
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pll_avl_clk <= wire_ddr3_pll0_generic_pll_pll6_68_outclk;
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pll_avl_phy_clk <= wire_ddr3_pll0_generic_pll_pll6_phy_70_outclk;
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pll_config_clk <= wire_ddr3_pll0_generic_pll_pll7_72_outclk;
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pll_locked <= wire_ddr3_pll0_generic_pll_pll1_56_locked;
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pll_mem_clk <= wire_ddr3_pll0_generic_pll_pll2_60_outclk;
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pll_mem_phy_clk <= wire_ddr3_pll0_generic_pll_pll2_phy_62_outclk;
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pll_write_clk <= wire_ddr3_pll0_generic_pll_pll3_64_outclk;
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pll_write_clk_pre_phy_clk <= wire_ddr3_pll0_generic_pll_pll3_64_outclk;
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wire_ddr3_pll0_generic_pll_pll1_56_rst <= wire_w_lg_global_reset_n1w(0);
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ddr3_pll0_generic_pll_pll1_56 : generic_pll
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GENERIC MAP (
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duty_cycle => 50,
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output_clock_frequency => "3334 ps",
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phase_shift => "0 ps",
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reference_clock_frequency => "50.0 MHz"
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)
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PORT MAP (
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fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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fboutclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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locked => wire_ddr3_pll0_generic_pll_pll1_56_locked,
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outclk => wire_ddr3_pll0_generic_pll_pll1_56_outclk,
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refclk => pll_ref_clk,
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rst => wire_ddr3_pll0_generic_pll_pll1_56_rst
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);
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wire_ddr3_pll0_generic_pll_pll1_phy_58_rst <= wire_w_lg_global_reset_n1w(0);
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ddr3_pll0_generic_pll_pll1_phy_58 : generic_pll
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GENERIC MAP (
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duty_cycle => 50,
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output_clock_frequency => "3334 ps",
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phase_shift => "0 ps",
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reference_clock_frequency => "50.0 MHz"
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)
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PORT MAP (
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fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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outclk => wire_ddr3_pll0_generic_pll_pll1_phy_58_outclk,
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refclk => pll_ref_clk,
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rst => wire_ddr3_pll0_generic_pll_pll1_phy_58_rst
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);
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wire_ddr3_pll0_generic_pll_pll2_60_rst <= wire_w_lg_global_reset_n1w(0);
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ddr3_pll0_generic_pll_pll2_60 : generic_pll
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GENERIC MAP (
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duty_cycle => 50,
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output_clock_frequency => "3334 ps",
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phase_shift => "0 ps",
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reference_clock_frequency => "50.0 MHz"
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)
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PORT MAP (
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fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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outclk => wire_ddr3_pll0_generic_pll_pll2_60_outclk,
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refclk => pll_ref_clk,
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rst => wire_ddr3_pll0_generic_pll_pll2_60_rst
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);
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wire_ddr3_pll0_generic_pll_pll2_phy_62_rst <= wire_w_lg_global_reset_n1w(0);
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ddr3_pll0_generic_pll_pll2_phy_62 : generic_pll
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GENERIC MAP (
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duty_cycle => 50,
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output_clock_frequency => "3334 ps",
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phase_shift => "0 ps",
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reference_clock_frequency => "50.0 MHz"
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)
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PORT MAP (
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fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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outclk => wire_ddr3_pll0_generic_pll_pll2_phy_62_outclk,
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refclk => pll_ref_clk,
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rst => wire_ddr3_pll0_generic_pll_pll2_phy_62_rst
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);
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wire_ddr3_pll0_generic_pll_pll3_64_rst <= wire_w_lg_global_reset_n1w(0);
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ddr3_pll0_generic_pll_pll3_64 : generic_pll
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GENERIC MAP (
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duty_cycle => 50,
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output_clock_frequency => "3334 ps",
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phase_shift => "2500 ps",
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reference_clock_frequency => "50.0 MHz"
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)
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PORT MAP (
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fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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outclk => wire_ddr3_pll0_generic_pll_pll3_64_outclk,
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refclk => pll_ref_clk,
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rst => wire_ddr3_pll0_generic_pll_pll3_64_rst
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);
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wire_ddr3_pll0_generic_pll_pll4_66_rst <= wire_w_lg_global_reset_n1w(0);
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ddr3_pll0_generic_pll_pll4_66 : generic_pll
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GENERIC MAP (
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duty_cycle => 50,
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output_clock_frequency => "3334 ps",
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phase_shift => "2500 ps",
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reference_clock_frequency => "50.0 MHz"
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)
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PORT MAP (
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fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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outclk => wire_ddr3_pll0_generic_pll_pll4_66_outclk,
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refclk => pll_ref_clk,
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rst => wire_ddr3_pll0_generic_pll_pll4_66_rst
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);
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wire_ddr3_pll0_generic_pll_pll6_68_rst <= wire_w_lg_global_reset_n1w(0);
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ddr3_pll0_generic_pll_pll6_68 : generic_pll
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GENERIC MAP (
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duty_cycle => 50,
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output_clock_frequency => "16670 ps",
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phase_shift => "416 ps",
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reference_clock_frequency => "50.0 MHz"
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)
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PORT MAP (
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fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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outclk => wire_ddr3_pll0_generic_pll_pll6_68_outclk,
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refclk => pll_ref_clk,
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rst => wire_ddr3_pll0_generic_pll_pll6_68_rst
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);
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wire_ddr3_pll0_generic_pll_pll6_phy_70_rst <= wire_w_lg_global_reset_n1w(0);
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ddr3_pll0_generic_pll_pll6_phy_70 : generic_pll
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GENERIC MAP (
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duty_cycle => 50,
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output_clock_frequency => "16670 ps",
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phase_shift => "416 ps",
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reference_clock_frequency => "50.0 MHz"
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)
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PORT MAP (
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fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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outclk => wire_ddr3_pll0_generic_pll_pll6_phy_70_outclk,
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refclk => pll_ref_clk,
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rst => wire_ddr3_pll0_generic_pll_pll6_phy_70_rst
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);
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wire_ddr3_pll0_generic_pll_pll7_72_rst <= wire_w_lg_global_reset_n1w(0);
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ddr3_pll0_generic_pll_pll7_72 : generic_pll
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GENERIC MAP (
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duty_cycle => 50,
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output_clock_frequency => "50010 ps",
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phase_shift => "0 ps",
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reference_clock_frequency => "50.0 MHz"
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)
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PORT MAP (
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fbclk => wire_ddr3_pll0_generic_pll_pll1_56_fboutclk,
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outclk => wire_ddr3_pll0_generic_pll_pll7_72_outclk,
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refclk => pll_ref_clk,
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rst => wire_ddr3_pll0_generic_pll_pll7_72_rst
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);
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END RTL; --ddr3_pll0
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--synopsys translate_on
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--VALID FILE
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