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mor1kx-bemicrocv/quartus/mor1kx-bemicrocv.qsf

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Initial commit
2016-08-04 19:22:38 +02:00
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
# Date created = 21:47:28 June 10, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# mor1kx-bemicrocv_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_location_assignment PIN_T22 -to jinn_uart_rx
set_location_assignment PIN_T15 -to jinn_uart_tx
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to jinn_uart_rx
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to jinn_uart_tx
set_location_assignment PIN_N1 -to GPIOA[0]
set_location_assignment PIN_N2 -to GPIOA[1]
set_location_assignment PIN_U1 -to GPIOA[2]
set_location_assignment PIN_U2 -to GPIOA[3]
set_location_assignment PIN_W2 -to GPIOA[4]
set_location_assignment PIN_AA1 -to GPIOA[5]
set_location_assignment PIN_AA2 -to GPIOA[6]
set_location_assignment PIN_Y3 -to GPIOA[7]
set_location_assignment PIN_R22 -to uart_rx
set_location_assignment PIN_R15 -to uart_tx
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_rx
set_instance_assignment -name IO_STANDARD "2.5 V" -to GPIOA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_tx
set_instance_assignment -name IO_STANDARD "SSTL-15" -to oct_rzqin -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[0] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[1] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[2] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[3] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[4] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[5] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[6] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[7] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[8] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[9] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[10] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[11] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[12] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[13] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[14] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[15] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[0] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ddr3_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs[0] -tag __ddr3_p0
set_instance_assignment -name D6_DELAY 0 -to mem_dqs[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[1] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ddr3_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs[1] -tag __ddr3_p0
set_instance_assignment -name D6_DELAY 0 -to mem_dqs[1] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[0] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ddr3_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs_n[0] -tag __ddr3_p0
set_instance_assignment -name D6_DELAY 0 -to mem_dqs_n[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[1] -tag __ddr3_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ddr3_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs_n[1] -tag __ddr3_p0
set_instance_assignment -name D6_DELAY 0 -to mem_dqs_n[1] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck[0] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck[0] -tag __ddr3_p0
set_instance_assignment -name D5_DELAY 2 -to mem_ck[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck_n[0] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck_n[0] -tag __ddr3_p0
set_instance_assignment -name D5_DELAY 2 -to mem_ck_n[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[0] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[10] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[10] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[11] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[11] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[12] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[12] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[1] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[1] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[2] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[2] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[3] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[3] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[4] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[4] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[5] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[5] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[6] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[6] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[7] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[7] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[8] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[8] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[9] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[9] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[0] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[1] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[1] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[2] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[2] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cas_n[0] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cas_n[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cke[0] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cke[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cs_n[0] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cs_n[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_odt[0] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_odt[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ras_n[0] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ras_n[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_we_n[0] -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_we_n[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD 1.5V -to mem_reset_n -tag __ddr3_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_reset_n -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[0] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[0] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[1] -tag __ddr3_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[1] -tag __ddr3_p0
set_instance_assignment -name IO_STANDARD "1.8 V" -to clk_hw
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[1] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[2] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[3] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[4] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[5] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[6] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[7] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[8] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[9] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[10] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[11] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[12] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[13] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[14] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[15] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[1] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[1] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[1] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[10] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[11] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[12] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[1] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[2] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[3] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[4] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[5] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[6] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[7] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[8] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[9] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[1] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[2] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cas_n[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cke[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cs_n[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_odt[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ras_n[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_we_n[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_reset_n -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck[0] -tag __ddr3_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck_n[0] -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to ddr3_inst|ddr3_inst|pll0|pll_avl_clk -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to ddr3_inst|ddr3_inst|pll0|pll_config_clk -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|ureset|phy_reset_n -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -tag __ddr3_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to ddr3_inst|ddr3_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __ddr3_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to ddr3_inst|ddr3_inst -tag __ddr3_p0
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to ddr3_inst|ddr3_inst|pll0|fbout -tag __ddr3_p0
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name ECO_REGENERATE_REPORT ON
set_location_assignment PIN_L7 -to mem_a[0]
set_location_assignment PIN_K7 -to mem_a[1]
set_location_assignment PIN_H8 -to mem_a[2]
set_location_assignment PIN_G8 -to mem_a[3]
set_location_assignment PIN_J7 -to mem_a[4]
set_location_assignment PIN_J8 -to mem_a[5]
set_location_assignment PIN_A10 -to mem_a[6]
set_location_assignment PIN_A9 -to mem_a[7]
set_location_assignment PIN_A8 -to mem_a[8]
set_location_assignment PIN_A7 -to mem_a[9]
set_location_assignment PIN_C6 -to mem_a[10]
set_location_assignment PIN_D6 -to mem_a[11]
set_location_assignment PIN_D7 -to mem_a[12]
set_location_assignment PIN_A5 -to mem_ba[0]
set_location_assignment PIN_B10 -to mem_ba[1]
set_location_assignment PIN_C9 -to mem_ba[2]
set_location_assignment PIN_B6 -to mem_cas_n[0]
set_location_assignment PIN_J9 -to mem_ck[0]
set_location_assignment PIN_H9 -to mem_ck_n[0]
set_location_assignment PIN_F14 -to mem_cke[0]
set_location_assignment PIN_E9 -to mem_cs_n[0]
set_location_assignment PIN_G11 -to mem_dm[0]
set_location_assignment PIN_J17 -to mem_dm[1]
set_location_assignment PIN_E12 -to mem_dq[0]
set_location_assignment PIN_D12 -to mem_dq[1]
set_location_assignment PIN_C11 -to mem_dq[2]
set_location_assignment PIN_K9 -to mem_dq[3]
set_location_assignment PIN_C13 -to mem_dq[4]
set_location_assignment PIN_D13 -to mem_dq[5]
set_location_assignment PIN_B12 -to mem_dq[6]
set_location_assignment PIN_F12 -to mem_dq[7]
set_location_assignment PIN_F13 -to mem_dq[8]
set_location_assignment PIN_E14 -to mem_dq[9]
set_location_assignment PIN_J11 -to mem_dq[10]
set_location_assignment PIN_A13 -to mem_dq[11]
set_location_assignment PIN_B15 -to mem_dq[12]
set_location_assignment PIN_C15 -to mem_dq[13]
set_location_assignment PIN_G15 -to mem_dq[14]
set_location_assignment PIN_K16 -to mem_dq[15]
set_location_assignment PIN_H11 -to mem_dqs[0]
set_location_assignment PIN_G12 -to mem_dqs_n[0]
set_location_assignment PIN_H14 -to mem_dqs[1]
set_location_assignment PIN_J13 -to mem_dqs_n[1]
set_location_assignment PIN_L8 -to mem_odt[0]
set_location_assignment PIN_B7 -to mem_ras_n[0]
set_location_assignment PIN_J19 -to mem_reset_n
set_location_assignment PIN_F7 -to mem_we_n[0]
set_location_assignment PIN_B11 -to oct_rzqin
set_location_assignment PIN_H18 -to rst_hw
set_location_assignment PIN_H13 -to clk_hw
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEFA2F23C7
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:47:28 JUNE 10, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "1.5 V" -to rst_hw
Rewrote SPI PHY -> Flash ROM works now
2017-03-01 19:08:01 +01:00
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_location_assignment PIN_U10 -to flash_cs_n
set_location_assignment PIN_T9 -to flash_reset_n
set_location_assignment PIN_N16 -to flash_sck
set_location_assignment PIN_M16 -to flash_si
set_location_assignment PIN_M18 -to flash_so
set_location_assignment PIN_N19 -to flash_wp_n
Added prelim. GPIO
2017-03-02 08:51:53 +01:00
set_global_assignment -name VHDL_FILE ../cores/gpio/gpio.vhd
Rewrote SPI PHY -> Flash ROM works now
2017-03-01 19:08:01 +01:00
set_global_assignment -name VHDL_FILE ../cores/generic/fancy_spi_master.vhd
set_global_assignment -name VHDL_FILE "../cores/flashrom-wb/flashrom_wb.vhd"
set_global_assignment -name VHDL_FILE "../cores/flashrom-wb/flashrom_pkg.vhd"
set_global_assignment -name VHDL_FILE "../cores/flashrom-wb/flashrom_controller.vhd"
Initial commit
2016-08-04 19:22:38 +02:00
set_global_assignment -name SDC_FILE "mor1kx-bemicrocv.out.sdc"
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_espresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_cappuccino.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_true_dpram_sclk.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ticktimer.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_store_buffer.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_simple_dpram_sclk.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_espresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_rf_cappuccino.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_pic.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_espresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_lsu_cappuccino.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_immu.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_icache.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_prontoespresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_espresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_fetch_cappuccino.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_execute_alu.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dmmu.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode_execute_cappuccino.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_decode.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_dcache.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_prontoespresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_espresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_ctrl_cappuccino.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_prontoespresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_espresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu_cappuccino.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cpu.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cfgrs.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_cache_lru.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_wb32.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_bus_if_avalon.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_branch_prediction.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-sprs.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx-defines.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx.v" -library mor1kx
set_global_assignment -name QIP_FILE ../ip/altera/ram0.qip
set_global_assignment -name VHDL_FILE "../ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_pkg.vhd" -library ip
set_global_assignment -name VHDL_FILE "../ip/mor1kx-mor1kx_v4/rtl/vhdl/mor1kx_vhdl.vhd" -library ip
set_global_assignment -name VHDL_FILE ../cores/jinn.vhd
set_global_assignment -name VHDL_FILE ../cores/uart/uart_wb.vhd
set_global_assignment -name VHDL_FILE ../cores/uart/uart_tx.vhd
set_global_assignment -name VHDL_FILE ../cores/uart/uart_rx.vhd
set_global_assignment -name VHDL_FILE ../cores/sram/sram_wb.vhd
set_global_assignment -name VHDL_FILE ../cores/generic/synchronizer.vhd
set_global_assignment -name VHDL_FILE ../cores/generic/edgeDetector.vhd
set_global_assignment -name VHDL_FILE ../design/top.vhd
set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/wishbone_package.vhd -library ip
set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/crossbar_v3.vhd -library ip
set_global_assignment -name QIP_FILE ../ip/altera/ddr3.qip
Added prelim. GPIO
2017-03-02 08:51:53 +01:00
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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