85 lines
2.4 KiB
VHDL
85 lines
2.4 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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library ip;
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use ip.wishbone_package.all;
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entity bench_top is
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end entity bench_top;
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architecture RTL of bench_top is
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signal clk_hw : std_logic;
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signal rst_hw : std_logic;
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signal GPIOA : std_logic_vector(wishbone_data_width - 1 downto 0);
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signal jinn_uart_rx : std_logic;
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signal jinn_uart_tx : std_logic;
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signal uart_rx : std_logic;
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signal uart_tx : std_logic;
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-- DDR3
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signal mem_a : std_logic_vector(12 downto 0);
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signal mem_ba : std_logic_vector(2 downto 0);
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signal mem_ck : std_logic_vector(0 downto 0);
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signal mem_ck_n : std_logic_vector(0 downto 0);
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signal mem_cke : std_logic_vector(0 downto 0);
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signal mem_cs_n : std_logic_vector(0 downto 0);
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signal mem_dm : std_logic_vector(1 downto 0);
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signal mem_ras_n : std_logic_vector(0 downto 0);
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signal mem_cas_n : std_logic_vector(0 downto 0);
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signal mem_we_n : std_logic_vector(0 downto 0);
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signal mem_reset_n : std_logic;
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signal mem_dq : std_logic_vector(15 downto 0);
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signal mem_dqs : std_logic_vector(1 downto 0);
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signal mem_dqs_n : std_logic_vector(1 downto 0);
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signal mem_odt : std_logic_vector(0 downto 0);
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signal oct_rzqin : std_logic;
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begin
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top_inst : entity design.top
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port map(
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clk_hw => clk_hw,
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rst_hw => rst_hw,
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GPIOA => GPIOA,
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jinn_uart_rx => jinn_uart_rx,
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jinn_uart_tx => jinn_uart_tx,
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uart_rx => uart_rx,
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uart_tx => uart_tx,
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mem_a => mem_a,
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mem_ba => mem_ba,
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mem_ck => mem_ck,
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mem_ck_n => mem_ck_n,
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mem_cke => mem_cke,
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mem_cs_n => mem_cs_n,
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mem_dm => mem_dm,
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mem_ras_n => mem_ras_n,
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mem_cas_n => mem_cas_n,
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mem_we_n => mem_we_n,
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mem_reset_n => mem_reset_n,
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mem_dq => mem_dq,
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mem_dqs => mem_dqs,
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mem_dqs_n => mem_dqs_n,
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mem_odt => mem_odt,
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oct_rzqin => oct_rzqin
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);
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clock_driver : process
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constant period : time := 10 ns;
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begin
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clk_hw <= '0';
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wait for period / 2;
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clk_hw <= '1';
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wait for period / 2;
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end process clock_driver;
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test : process is
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begin
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rst_hw <= '0';
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wait for 50 ns;
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rst_hw <= '1';
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wait;
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end process test;
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end architecture RTL;
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