105 lines
2.6 KiB
VHDL
105 lines
2.6 KiB
VHDL
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-- A simple UART (TX)
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-- Author : Kurisu <kurisu@shimatta.de>
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-- Modifed : Markus <markus-oliver.koch@thalesgroup.com>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity uart_tx is
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port(
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clk : in std_logic;
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rst : in std_logic;
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data : in std_logic_vector(7 downto 0);
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byte_ready : in std_logic;
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busy : out std_logic;
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ckDiv : in std_logic_vector(15 downto 0);
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parityEnable : in std_logic;
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parityOdd : in std_logic;
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twoStopBits : in std_logic;
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tx : out std_logic
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);
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end entity uart_tx;
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architecture RTL of uart_tx is
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type state_t is (IDLE, START, TRANSMIT, PARITY, STOP);
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signal state : state_t;
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signal clkDivider : unsigned(15 downto 0);
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signal data_i : std_logic_vector(7 downto 0);
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signal bitCounter : integer range 0 to 7;
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signal parity_calc : std_logic;
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begin
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txFSM : process(clk, rst, ckDiv, parityOdd) is
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begin
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if rst = '1' then
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data_i <= x"00";
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state <= IDLE;
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tx <= '1';
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bitCounter <= 0;
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busy <= '0';
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clkDivider <= unsigned(ckDiv);
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parity_calc <= parityOdd;
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elsif rising_edge(clk) then
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busy <= '1';
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if (clkDivider = 0) then
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clkDivider <= unsigned(ckDiv);
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else
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clkDivider <= clkDivider - 1;
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end if;
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case state is
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when IDLE =>
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busy <= '0';
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tx <= '1';
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if byte_ready = '1' then
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data_i <= data;
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state <= START;
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clkDivider <= unsigned(ckDiv);
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bitCounter <= 0;
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parity_calc <= '0';
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busy <= '1';
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tx <= '1';
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end if;
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when START =>
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tx <= '0';
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state <= TRANSMIT;
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when TRANSMIT =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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tx <= data_i(bitCounter);
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if data_i(bitCounter) = '1' then
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parity_calc <= not parity_calc;
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end if;
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if bitCounter = 7 then
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bitCounter <= 0;
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if parityEnable = '1' then
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state <= PARITY;
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else
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state <= STOP;
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end if;
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else
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bitCounter <= bitCounter + 1;
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end if;
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end if;
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when PARITY =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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tx <= parity_calc;
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state <= STOP;
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end if;
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when STOP =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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tx <= '1';
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bitCounter <= bitCounter + 1;
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if (bitCounter = 1 and twoStopBits = '0') or (bitCounter = 2 and twoStopBits = '1') then
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state <= IDLE;
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end if;
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end if;
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end case;
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end if;
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end process txFSM;
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end architecture RTL;
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