75 lines
1.9 KiB
VHDL
75 lines
1.9 KiB
VHDL
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-- TODO: This is only a placeholder for a "real" GPIO core.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library ip;
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use ip.wishbone_package.all;
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entity gpio is
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port(
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clk : in std_logic;
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rst : in std_logic;
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clr : in std_logic;
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-- Wishbone
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wb_in : in wishbone_v3_slave_in;
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wb_out : out wishbone_v3_slave_out;
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-- Ports
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gpio : inout std_logic_vector(31 downto 0)
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);
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end entity gpio;
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architecture RTL of gpio is
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signal reg_port : std_logic_vector(31 downto 0);
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signal reg_ddr : std_logic_vector(31 downto 0);
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begin
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gpio_p : process(clk, rst) is
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procedure default_state is
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begin
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null;
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end procedure default_state;
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procedure reset_state is
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begin
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default_state;
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reg_ddr <= (others => '0');
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reg_port <= (others => '0');
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end procedure reset_state;
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begin
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if rst = '1' then
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reset_state;
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elsif rising_edge(clk) then
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default_state;
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if clr = '1' then
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reset_state;
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else
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if (wb_in.STB = '1' and wb_in.CYC = '1' and wb_in.WE = '1') then
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for i in 0 to 3 loop
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if (wb_in.SEL(i) = '1') then
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case wb_in.ADR(3 downto 2) is
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when "00" => reg_ddr((i + 1) * 8 - 1 downto i * 8) <= wb_in.DAT((i + 1) * 8 - 1 downto i * 8);
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when "01" => reg_port((i + 1) * 8 - 1 downto i * 8) <= wb_in.DAT((i + 1) * 8 - 1 downto i * 8);
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when others => null;
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end case;
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end if;
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end loop;
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end if;
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end if;
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end if;
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end process gpio_p;
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wb_out.ERR <= '0';
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wb_out.RTY <= '0';
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wb_out.ACK <= (wb_in.STB and wb_in.CYC);
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read : with wb_in.ADR(3 downto 2) select wb_out.DAT <=
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reg_ddr when "00",
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reg_port when "01",
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gpio when others;
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writeport : for i in 0 to 31 generate
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gpio(i) <= reg_port(i) when reg_ddr(i) = '1' else 'Z';
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end generate writeport;
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end architecture RTL;
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