439 lines
14 KiB
Systemverilog
439 lines
14 KiB
Systemverilog
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// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// ********************************************************************************************************************************
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// This file instantiates the PLL.
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// ********************************************************************************************************************************
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`timescale 1 ps / 1 ps
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(* altera_attribute = "-name IP_TOOL_NAME common; -name IP_TOOL_VERSION 15.1; -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 100; -name ALLOW_SYNCH_CTRL_USAGE OFF; -name AUTO_CLOCK_ENABLE_RECOGNITION OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
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module ddr3_pll0 (
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global_reset_n,
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pll_ref_clk,
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pll_mem_clk,
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pll_write_clk,
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pll_write_clk_pre_phy_clk,
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pll_addr_cmd_clk,
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pll_avl_clk,
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pll_config_clk,
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pll_locked,
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afi_half_clk,
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pll_mem_phy_clk,
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afi_phy_clk,
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pll_avl_phy_clk,
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afi_clk
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);
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// ********************************************************************************************************************************
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// BEGIN PARAMETER SECTION
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// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver.
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parameter DEVICE_FAMILY = "Cyclone V";
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// choose between abstract (fast) and regular model
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`ifndef ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL
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`define ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL 0
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`endif
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parameter ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL = `ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
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localparam FAST_SIM_MODEL = ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL;
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// Clock settings
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parameter REF_CLK_FREQ = "50.0 MHz";
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parameter REF_CLK_PERIOD_PS = 20000;
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parameter PLL_AFI_CLK_FREQ_STR = "300.0 MHz";
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parameter PLL_MEM_CLK_FREQ_STR = "300.0 MHz";
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parameter PLL_WRITE_CLK_FREQ_STR = "300.0 MHz";
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parameter PLL_ADDR_CMD_CLK_FREQ_STR = "300.0 MHz";
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parameter PLL_AFI_HALF_CLK_FREQ_STR = "150.0 MHz";
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parameter PLL_NIOS_CLK_FREQ_STR = "60.0 MHz";
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parameter PLL_CONFIG_CLK_FREQ_STR = "20.0 MHz";
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parameter PLL_P2C_READ_CLK_FREQ_STR = "";
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parameter PLL_C2P_WRITE_CLK_FREQ_STR = "";
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parameter PLL_HR_CLK_FREQ_STR = "";
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parameter PLL_DR_CLK_FREQ_STR = "";
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parameter PLL_AFI_CLK_FREQ_SIM_STR = "3334 ps";
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parameter PLL_MEM_CLK_FREQ_SIM_STR = "3334 ps";
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parameter PLL_WRITE_CLK_FREQ_SIM_STR = "3334 ps";
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parameter PLL_ADDR_CMD_CLK_FREQ_SIM_STR = "3334 ps";
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parameter PLL_AFI_HALF_CLK_FREQ_SIM_STR = "6668 ps";
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parameter PLL_NIOS_CLK_FREQ_SIM_STR = "16670 ps";
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parameter PLL_CONFIG_CLK_FREQ_SIM_STR = "50010 ps";
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parameter PLL_P2C_READ_CLK_FREQ_SIM_STR = "0 ps";
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parameter PLL_C2P_WRITE_CLK_FREQ_SIM_STR = "0 ps";
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parameter PLL_HR_CLK_FREQ_SIM_STR = "0 ps";
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parameter PLL_DR_CLK_FREQ_SIM_STR = "0 ps";
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parameter AFI_CLK_PHASE = "0 ps";
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parameter AFI_PHY_CLK_PHASE = "0 ps";
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parameter MEM_CLK_PHASE = "0 ps";
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parameter WRITE_CLK_PHASE = "2500 ps";
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parameter ADDR_CMD_CLK_PHASE = "2500 ps";
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parameter AFI_HALF_CLK_PHASE = "0 ps";
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parameter AVL_CLK_PHASE = "416 ps";
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parameter CONFIG_CLK_PHASE = "0 ps";
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parameter MEM_CLK_PHASE_SIM = "0 ps";
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parameter WRITE_CLK_PHASE_SIM = "2500 ps";
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parameter ADDR_CMD_CLK_PHASE_SIM = "2500 ps";
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parameter ABSTRACT_REAL_COMPARE_TEST = "false";
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localparam SIM_FILESET = ("false" == "true");
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localparam AFI_CLK_FREQ = SIM_FILESET ? PLL_AFI_CLK_FREQ_SIM_STR : PLL_AFI_CLK_FREQ_STR;
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localparam MEM_CLK_FREQ = SIM_FILESET ? PLL_MEM_CLK_FREQ_SIM_STR : PLL_MEM_CLK_FREQ_STR;
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localparam WRITE_CLK_FREQ = SIM_FILESET ? PLL_WRITE_CLK_FREQ_SIM_STR : PLL_WRITE_CLK_FREQ_STR;
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localparam ADDR_CMD_CLK_FREQ = SIM_FILESET ? PLL_ADDR_CMD_CLK_FREQ_SIM_STR : PLL_ADDR_CMD_CLK_FREQ_STR;
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localparam AFI_HALF_CLK_FREQ = SIM_FILESET ? PLL_AFI_HALF_CLK_FREQ_SIM_STR : PLL_AFI_HALF_CLK_FREQ_STR;
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localparam AVL_CLK_FREQ = SIM_FILESET ? PLL_NIOS_CLK_FREQ_SIM_STR : PLL_NIOS_CLK_FREQ_STR;
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localparam CONFIG_CLK_FREQ = SIM_FILESET ? PLL_CONFIG_CLK_FREQ_SIM_STR : PLL_CONFIG_CLK_FREQ_STR;
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localparam P2C_READ_CLK_FREQ = SIM_FILESET ? PLL_P2C_READ_CLK_FREQ_SIM_STR : PLL_P2C_READ_CLK_FREQ_STR;
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localparam C2P_WRITE_CLK_FREQ = SIM_FILESET ? PLL_C2P_WRITE_CLK_FREQ_SIM_STR : PLL_C2P_WRITE_CLK_FREQ_STR;
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localparam HR_CLK_FREQ = SIM_FILESET ? PLL_HR_CLK_FREQ_SIM_STR : PLL_HR_CLK_FREQ_STR;
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localparam DR_CLK_FREQ = SIM_FILESET ? PLL_DR_CLK_FREQ_SIM_STR : PLL_DR_CLK_FREQ_STR;
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// END PARAMETER SECTION
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// ********************************************************************************************************************************
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// ********************************************************************************************************************************
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// BEGIN PORT SECTION
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input pll_ref_clk; // PLL reference clock
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// When the PHY is selected to be a PLL/DLL MASTER, the PLL and DLL are instantied on this top level
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wire pll_afi_clk /* synthesis keep */; // See pll_memphy instantiation below for detailed description of each clock
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output pll_mem_clk;
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output pll_write_clk;
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output pll_write_clk_pre_phy_clk;
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output pll_addr_cmd_clk;
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output pll_avl_clk;
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output pll_config_clk;
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output pll_locked; // When 0, PLL is out of lock
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// should be used to reset system level afi_clk domain logic
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// Reset Interface, AFI 2.0
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input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
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// PLL Interface
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output afi_clk;
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output afi_half_clk;
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output pll_mem_phy_clk;
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output afi_phy_clk;
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output pll_avl_phy_clk;
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// END PARAMETER SECTION
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// ********************************************************************************************************************************
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initial $display("Using %0s pll emif simulation models", FAST_SIM_MODEL ? "Fast" : "Regular");
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wire fbout;
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generic_pll pll1 (
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.refclk({pll_ref_clk}),
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.rst(~global_reset_n),
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.fbclk(fbout),
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.outclk(pll_afi_clk),
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.fboutclk(fbout),
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.locked(pll_locked),
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.writerefclkdata(),
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.writeoutclkdata(),
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.writephaseshiftdata(),
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.writedutycycledata(),
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.readrefclkdata(),
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.readoutclkdata(),
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.readphaseshiftdata(),
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.readdutycycledata()
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);
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defparam pll1.reference_clock_frequency = REF_CLK_FREQ,
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pll1.output_clock_frequency = AFI_CLK_FREQ,
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pll1.phase_shift = AFI_CLK_PHASE,
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pll1.duty_cycle = 50;
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generic_pll pll1_phy (
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.refclk({pll_ref_clk}),
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.rst(~global_reset_n),
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.fbclk(fbout),
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.outclk(afi_phy_clk),
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.fboutclk(),
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.locked(),
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.writerefclkdata(),
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.writeoutclkdata(),
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.writephaseshiftdata(),
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.writedutycycledata(),
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.readrefclkdata(),
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.readoutclkdata(),
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.readphaseshiftdata(),
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.readdutycycledata()
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);
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defparam pll1_phy.reference_clock_frequency = REF_CLK_FREQ;
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defparam pll1_phy.output_clock_frequency = AFI_CLK_FREQ;
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// The following is evaluated for RTL simulation
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// synthesis translate_off
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defparam pll1_phy.phase_shift = AFI_CLK_PHASE;
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// synthesis translate_on
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// The following is evaluated for physical realization
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// synthesis read_comments_as_HDL on
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`ifdef SYNTH_FOR_SIM
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// defparam pll1_phy.phase_shift = AFI_CLK_PHASE;
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`else
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// defparam pll1_phy.phase_shift = AFI_PHY_CLK_PHASE;
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`endif
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// synthesis read_comments_as_HDL off
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defparam pll1_phy.duty_cycle = 50;
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generic_pll pll2 (
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.refclk({pll_ref_clk}),
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.rst(~global_reset_n),
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.fbclk(fbout),
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.outclk(pll_mem_clk),
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.fboutclk(),
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.locked(),
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.writerefclkdata(),
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.writeoutclkdata(),
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.writephaseshiftdata(),
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.writedutycycledata(),
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.readrefclkdata(),
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.readoutclkdata(),
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.readphaseshiftdata(),
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.readdutycycledata()
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);
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defparam pll2.reference_clock_frequency = REF_CLK_FREQ;
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defparam pll2.output_clock_frequency = MEM_CLK_FREQ;
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// The following is evaluated for RTL simulation
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// synthesis translate_off
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defparam pll2.phase_shift = MEM_CLK_PHASE_SIM;
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// synthesis translate_on
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// The following is evaluated for physical realization
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// synthesis read_comments_as_HDL on
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`ifdef SYNTH_FOR_SIM
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// defparam pll2.phase_shift = MEM_CLK_PHASE_SIM;
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`else
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// defparam pll2.phase_shift = MEM_CLK_PHASE;
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`endif
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// synthesis read_comments_as_HDL off
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defparam pll2.duty_cycle = 50;
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generic_pll pll2_phy (
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.refclk({pll_ref_clk}),
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.rst(~global_reset_n),
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.fbclk(fbout),
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.outclk(pll_mem_phy_clk),
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.fboutclk(),
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.locked(),
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.writerefclkdata(),
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.writeoutclkdata(),
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.writephaseshiftdata(),
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.writedutycycledata(),
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.readrefclkdata(),
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.readoutclkdata(),
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.readphaseshiftdata(),
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.readdutycycledata()
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);
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defparam pll2_phy.reference_clock_frequency = REF_CLK_FREQ;
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defparam pll2_phy.output_clock_frequency = MEM_CLK_FREQ;
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// The following is evaluated for RTL simulation
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// synthesis translate_off
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defparam pll2_phy.phase_shift = MEM_CLK_PHASE_SIM;
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// synthesis translate_on
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// The following is evaluated for physical realization
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// synthesis read_comments_as_HDL on
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`ifdef SYNTH_FOR_SIM
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// defparam pll2_phy.phase_shift = MEM_CLK_PHASE_SIM;
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`else
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// defparam pll2_phy.phase_shift = MEM_CLK_PHASE;
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`endif
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// synthesis read_comments_as_HDL off
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defparam pll2_phy.duty_cycle = 50;
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generic_pll pll3 (
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.refclk({pll_ref_clk}),
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.rst(~global_reset_n),
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.fbclk(fbout),
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.outclk(pll_write_clk_pre_phy_clk),
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.fboutclk(),
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.locked(),
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.writerefclkdata(),
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.writeoutclkdata(),
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.writephaseshiftdata(),
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.writedutycycledata(),
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.readrefclkdata(),
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.readoutclkdata(),
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.readphaseshiftdata(),
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.readdutycycledata()
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);
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defparam pll3.reference_clock_frequency = REF_CLK_FREQ;
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defparam pll3.output_clock_frequency = WRITE_CLK_FREQ;
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// The following is evaluated for RTL simulation
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// synthesis translate_off
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defparam pll3.phase_shift = WRITE_CLK_PHASE_SIM;
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// synthesis translate_on
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// The following is evaluated for physical realization
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// synthesis read_comments_as_HDL on
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`ifdef SYNTH_FOR_SIM
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// defparam pll3.phase_shift = WRITE_CLK_PHASE_SIM;
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`else
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// defparam pll3.phase_shift = WRITE_CLK_PHASE;
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`endif
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// synthesis read_comments_as_HDL off
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defparam pll3.duty_cycle = 50;
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generic_pll pll4 (
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.refclk({pll_ref_clk}),
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.rst(~global_reset_n),
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.fbclk(fbout),
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.outclk(pll_addr_cmd_clk),
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.fboutclk(),
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.locked(),
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.writerefclkdata(),
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.writeoutclkdata(),
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.writephaseshiftdata(),
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.writedutycycledata(),
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.readrefclkdata(),
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.readoutclkdata(),
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.readphaseshiftdata(),
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.readdutycycledata()
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);
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defparam pll4.reference_clock_frequency = REF_CLK_FREQ;
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defparam pll4.output_clock_frequency = ADDR_CMD_CLK_FREQ;
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// The following is evaluated for RTL simulation
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// synthesis translate_off
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defparam pll4.phase_shift = ADDR_CMD_CLK_PHASE_SIM;
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// synthesis translate_on
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// The following is evaluated for physical realization
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// synthesis read_comments_as_HDL on
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`ifdef SYNTH_FOR_SIM
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// defparam pll4.phase_shift = ADDR_CMD_CLK_PHASE_SIM;
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`else
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|
// defparam pll4.phase_shift = ADDR_CMD_CLK_PHASE;
|
||
|
|
`endif
|
||
|
|
// synthesis read_comments_as_HDL off
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||
|
|
defparam pll4.duty_cycle = 50;
|
||
|
|
|
||
|
|
|
||
|
|
generic_pll pll6 (
|
||
|
|
.refclk({pll_ref_clk}),
|
||
|
|
.rst(~global_reset_n),
|
||
|
|
.fbclk(fbout),
|
||
|
|
.outclk(pll_avl_clk),
|
||
|
|
.fboutclk(),
|
||
|
|
.locked(),
|
||
|
|
.writerefclkdata(),
|
||
|
|
.writeoutclkdata(),
|
||
|
|
.writephaseshiftdata(),
|
||
|
|
.writedutycycledata(),
|
||
|
|
.readrefclkdata(),
|
||
|
|
.readoutclkdata(),
|
||
|
|
.readphaseshiftdata(),
|
||
|
|
.readdutycycledata()
|
||
|
|
);
|
||
|
|
defparam pll6.reference_clock_frequency = REF_CLK_FREQ,
|
||
|
|
pll6.output_clock_frequency = AVL_CLK_FREQ,
|
||
|
|
pll6.phase_shift = AVL_CLK_PHASE,
|
||
|
|
pll6.duty_cycle = 50;
|
||
|
|
|
||
|
|
generic_pll pll6_phy (
|
||
|
|
.refclk({pll_ref_clk}),
|
||
|
|
.rst(~global_reset_n),
|
||
|
|
.fbclk(fbout),
|
||
|
|
.outclk(pll_avl_phy_clk),
|
||
|
|
.fboutclk(),
|
||
|
|
.locked(),
|
||
|
|
.writerefclkdata(),
|
||
|
|
.writeoutclkdata(),
|
||
|
|
.writephaseshiftdata(),
|
||
|
|
.writedutycycledata(),
|
||
|
|
.readrefclkdata(),
|
||
|
|
.readoutclkdata(),
|
||
|
|
.readphaseshiftdata(),
|
||
|
|
.readdutycycledata()
|
||
|
|
);
|
||
|
|
defparam pll6_phy.reference_clock_frequency = REF_CLK_FREQ,
|
||
|
|
pll6_phy.output_clock_frequency = AVL_CLK_FREQ,
|
||
|
|
pll6_phy.phase_shift = AVL_CLK_PHASE,
|
||
|
|
pll6_phy.duty_cycle = 50;
|
||
|
|
|
||
|
|
generic_pll pll7 (
|
||
|
|
.refclk({pll_ref_clk}),
|
||
|
|
.rst(~global_reset_n),
|
||
|
|
.fbclk(fbout),
|
||
|
|
.outclk(pll_config_clk),
|
||
|
|
.fboutclk(),
|
||
|
|
.locked(),
|
||
|
|
.writerefclkdata(),
|
||
|
|
.writeoutclkdata(),
|
||
|
|
.writephaseshiftdata(),
|
||
|
|
.writedutycycledata(),
|
||
|
|
.readrefclkdata(),
|
||
|
|
.readoutclkdata(),
|
||
|
|
.readphaseshiftdata(),
|
||
|
|
.readdutycycledata()
|
||
|
|
);
|
||
|
|
defparam pll7.reference_clock_frequency = REF_CLK_FREQ,
|
||
|
|
pll7.output_clock_frequency = CONFIG_CLK_FREQ,
|
||
|
|
pll7.phase_shift = CONFIG_CLK_PHASE,
|
||
|
|
pll7.duty_cycle = 50;
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
`ifndef SIMGEN
|
||
|
|
assign pll_write_clk = pll_write_clk_pre_phy_clk;
|
||
|
|
`else
|
||
|
|
assign pll_write_clk = pll_write_clk_pre_phy_clk;
|
||
|
|
`endif
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
// Clock descriptions
|
||
|
|
// pll_afi_clk: full-rate clock, 0 degree phase shift, clock for AFI interface logic
|
||
|
|
// pll_mem_clk: full-rate clock, 0 degree phase shift, clock output to memory
|
||
|
|
// pll_write_clk: full-rate clock, -90 degree phase shift, clocks write data out to memory
|
||
|
|
// pll_addr_cmd_clk: full-rate clock, inverted version (180 degree phase shift) of pll_afi_clk, clocks address/command out to memory
|
||
|
|
// In the special case of QDRII, BL2, address/command is double data rate (same as write data)
|
||
|
|
// pll_addr_cmd_clk will have -90 degree phase shift (same as write clock)
|
||
|
|
// pll_afi_half_clk: half-rate clock, 0 degree phase shift
|
||
|
|
// the purpose of these clock settings is so that address/command/write data are centred aligned with the output clock(s) to memory
|
||
|
|
|
||
|
|
assign afi_clk = pll_afi_clk;
|
||
|
|
|
||
|
|
assign afi_half_clk = 1'b0;
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|