236 lines
9.6 KiB
Tcl
236 lines
9.6 KiB
Tcl
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# (C) 2001-2016 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and
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# other software and tools, and its AMPP partner logic functions, and
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# any output files any of the foregoing (including device programming
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# or simulation files), and any associated documentation or information
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# are expressly subject to the terms and conditions of the Altera
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# Program License Subscription Agreement, Altera MegaCore Function
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# License Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by Altera
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# or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# ACDS 15.1 185 linux 2016.01.17.15:36:30
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# ----------------------------------------
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# Auto-generated simulation script rivierapro_setup.tcl
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# ----------------------------------------
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# This script can be used to simulate the following IP:
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# ddr3
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# To create a top-level simulation script which compiles other
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# IP, and manages other system issues, copy the following template
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# and adapt it to your needs:
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#
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# # Start of template
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# # If the copied and modified template file is "aldec.do", run it as:
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# # vsim -c -do aldec.do
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# #
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# # Source the generated sim script
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# source rivierapro_setup.tcl
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# # Compile eda/sim_lib contents first
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# dev_com
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# # Override the top-level name (so that elab is useful)
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# set TOP_LEVEL_NAME top
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# # Compile the standalone IP.
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# com
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# # Compile the user top-level
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# vlog -sv2k5 ../../top.sv
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# # Elaborate the design.
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# elab
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# # Run the simulation
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# run
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# # Report success to the shell
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# exit -code 0
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# # End of template
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# ----------------------------------------
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# If ddr3 is one of several IP cores in your
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# Quartus project, you can generate a simulation script
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# suitable for inclusion in your top-level simulation
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# script by running the following command line:
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#
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# ip-setup-simulation --quartus-project=<quartus project>
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#
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# ip-setup-simulation will discover the Altera IP
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# within the Quartus project, and generate a unified
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# script which supports all the Altera IP within the design.
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# ----------------------------------------
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# ----------------------------------------
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# Initialize variables
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if ![info exists SYSTEM_INSTANCE_NAME] {
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set SYSTEM_INSTANCE_NAME ""
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} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
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set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
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}
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if ![info exists TOP_LEVEL_NAME] {
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set TOP_LEVEL_NAME "ddr3"
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}
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if ![info exists QSYS_SIMDIR] {
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set QSYS_SIMDIR "./../"
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}
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if ![info exists QUARTUS_INSTALL_DIR] {
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set QUARTUS_INSTALL_DIR "/opt/altera/15.1/quartus/"
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}
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if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
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set USER_DEFINED_COMPILE_OPTIONS ""
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}
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if ![info exists USER_DEFINED_ELAB_OPTIONS] {
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set USER_DEFINED_ELAB_OPTIONS ""
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}
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# ----------------------------------------
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# Initialize simulation properties - DO NOT MODIFY!
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set ELAB_OPTIONS ""
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set SIM_OPTIONS ""
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if ![ string match "*-64 vsim*" [ vsim -version ] ] {
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} else {
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}
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set Aldec "Riviera"
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if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
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set Aldec "Active"
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}
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if { [ string match "Active" $Aldec ] } {
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scripterconf -tcl
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createdesign "$TOP_LEVEL_NAME" "."
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opendesign "$TOP_LEVEL_NAME"
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}
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# ----------------------------------------
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# Copy ROM/RAM files to simulation directory
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alias file_copy {
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echo "\[exec\] file_copy"
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}
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# ----------------------------------------
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# Create compilation libraries
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proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
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ensure_lib ./libraries
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ensure_lib ./libraries/work
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vmap work ./libraries/work
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ensure_lib ./libraries/altera
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vmap altera ./libraries/altera
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ensure_lib ./libraries/lpm
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vmap lpm ./libraries/lpm
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ensure_lib ./libraries/sgate
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vmap sgate ./libraries/sgate
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ensure_lib ./libraries/altera_mf
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vmap altera_mf ./libraries/altera_mf
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ensure_lib ./libraries/altera_lnsim
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vmap altera_lnsim ./libraries/altera_lnsim
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ensure_lib ./libraries/cyclonev
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vmap cyclonev ./libraries/cyclonev
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ensure_lib ./libraries/pll0
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vmap pll0 ./libraries/pll0
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ensure_lib ./libraries/ddr3
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vmap ddr3 ./libraries/ddr3
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# ----------------------------------------
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# Compile device library files
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alias dev_com {
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echo "\[exec\] dev_com"
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eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd" -work altera
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd" -work altera
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd" -work altera
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd" -work altera
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd" -work altera
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd" -work lpm
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd" -work lpm
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd" -work sgate
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd" -work sgate
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd" -work altera_mf
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd" -work altera_mf
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vlog $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd" -work altera_lnsim
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vlog -v2k5 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd" -work cyclonev
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vcom $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd" -work cyclonev
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}
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# ----------------------------------------
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# Compile the design files in correct order
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alias com {
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echo "\[exec\] com"
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eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0.vho" -work pll0
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eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_pll0_sim_delay.vhd" -work pll0
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eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3/ddr3_0002.vhd" -work ddr3
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eval vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ddr3.vhd"
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}
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# ----------------------------------------
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# Elaborate top level design
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alias elab {
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echo "\[exec\] elab"
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eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L pll0 -L ddr3 -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
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}
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# ----------------------------------------
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# Elaborate the top level design with -dbg -O2 option
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alias elab_debug {
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echo "\[exec\] elab_debug"
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eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L pll0 -L ddr3 -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
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}
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# ----------------------------------------
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# Compile all the design files and elaborate the top level design
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alias ld "
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dev_com
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com
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elab
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"
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# ----------------------------------------
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# Compile all the design files and elaborate the top level design with -dbg -O2
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alias ld_debug "
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dev_com
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com
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elab_debug
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"
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# ----------------------------------------
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# Print out user commmand line aliases
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alias h {
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echo "List Of Command Line Aliases"
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echo
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echo "file_copy -- Copy ROM/RAM files to simulation directory"
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echo
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echo "dev_com -- Compile device library files"
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echo
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echo "com -- Compile the design files in correct order"
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echo
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echo "elab -- Elaborate top level design"
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echo
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echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
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echo
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echo "ld -- Compile all the design files and elaborate the top level design"
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echo
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echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
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echo
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echo
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echo
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echo "List Of Variables"
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echo
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echo "TOP_LEVEL_NAME -- Top level module name."
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echo " For most designs, this should be overridden"
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echo " to enable the elab/elab_debug aliases."
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echo
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echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
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echo
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echo "QSYS_SIMDIR -- Qsys base simulation directory."
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echo
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echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
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echo
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echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
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echo
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echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
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}
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file_copy
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h
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