2062 lines
181 KiB
VHDL
2062 lines
181 KiB
VHDL
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-- ddr3_0002.vhd
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-- This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl. If you edit it your changes
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-- will probably be lost.
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--
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-- Generated using ACDS version 15.1 185
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity ddr3_0002 is
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port (
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pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
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global_reset_n : in std_logic := '0'; -- global_reset.reset_n
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soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
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afi_clk : out std_logic; -- afi_clk.clk
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afi_half_clk : out std_logic; -- afi_half_clk.clk
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afi_reset_n : out std_logic; -- afi_reset.reset_n
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afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
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mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a
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mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
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mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck
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mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
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mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
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mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
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mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm
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mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
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mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
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mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
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mem_reset_n : out std_logic; -- .mem_reset_n
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mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq
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mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs
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mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n
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mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
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avl_ready_0 : out std_logic; -- avl_0.waitrequest_n
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avl_burstbegin_0 : in std_logic := '0'; -- .beginbursttransfer
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avl_addr_0 : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
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avl_rdata_valid_0 : out std_logic; -- .readdatavalid
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avl_rdata_0 : out std_logic_vector(31 downto 0); -- .readdata
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avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
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avl_be_0 : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
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avl_read_req_0 : in std_logic := '0'; -- .read
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avl_write_req_0 : in std_logic := '0'; -- .write
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avl_size_0 : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
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mp_cmd_clk_0_clk : in std_logic := '0'; -- mp_cmd_clk_0.clk
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mp_cmd_reset_n_0_reset_n : in std_logic := '0'; -- mp_cmd_reset_n_0.reset_n
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mp_rfifo_clk_0_clk : in std_logic := '0'; -- mp_rfifo_clk_0.clk
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mp_rfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_rfifo_reset_n_0.reset_n
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mp_wfifo_clk_0_clk : in std_logic := '0'; -- mp_wfifo_clk_0.clk
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mp_wfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_wfifo_reset_n_0.reset_n
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csr_clk : in std_logic := '0'; -- csr_clk.clk
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csr_reset_n : in std_logic := '0'; -- csr_reset_n.reset_n
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local_init_done : out std_logic; -- status.local_init_done
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local_cal_success : out std_logic; -- .local_cal_success
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local_cal_fail : out std_logic; -- .local_cal_fail
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oct_rzqin : in std_logic := '0'; -- oct.rzqin
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pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
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pll_write_clk : out std_logic; -- .pll_write_clk
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pll_locked : out std_logic; -- .pll_locked
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pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
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pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
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pll_avl_clk : out std_logic; -- .pll_avl_clk
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pll_config_clk : out std_logic; -- .pll_config_clk
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pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk
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afi_phy_clk : out std_logic; -- .afi_phy_clk
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pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk
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);
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end entity ddr3_0002;
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architecture rtl of ddr3_0002 is
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component ddr3_pll0 is
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port (
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global_reset_n : in std_logic := 'X'; -- reset_n
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afi_clk : out std_logic; -- clk
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afi_half_clk : out std_logic; -- clk
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pll_ref_clk : in std_logic := 'X'; -- clk
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pll_mem_clk : out std_logic; -- pll_mem_clk
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pll_write_clk : out std_logic; -- pll_write_clk
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pll_locked : out std_logic; -- pll_locked
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pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
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pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
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pll_avl_clk : out std_logic; -- pll_avl_clk
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pll_config_clk : out std_logic; -- pll_config_clk
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pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
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afi_phy_clk : out std_logic; -- afi_phy_clk
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pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
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);
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end component ddr3_pll0;
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component ddr3_p0 is
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port (
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global_reset_n : in std_logic := 'X'; -- reset_n
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soft_reset_n : in std_logic := 'X'; -- reset_n
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csr_soft_reset_req : in std_logic := 'X'; -- reset
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afi_reset_n : out std_logic; -- reset_n
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afi_reset_export_n : out std_logic; -- reset_n
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ctl_reset_n : out std_logic; -- reset_n
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afi_clk : in std_logic := 'X'; -- clk
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afi_half_clk : in std_logic := 'X'; -- clk
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ctl_clk : out std_logic; -- clk
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avl_clk : out std_logic; -- clk
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avl_reset_n : out std_logic; -- reset_n
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scc_clk : out std_logic; -- clk
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scc_reset_n : out std_logic; -- reset_n
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avl_address : in std_logic_vector(15 downto 0) := (others => 'X'); -- address
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avl_write : in std_logic := 'X'; -- write
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avl_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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avl_read : in std_logic := 'X'; -- read
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avl_readdata : out std_logic_vector(31 downto 0); -- readdata
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avl_waitrequest : out std_logic; -- waitrequest
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dll_clk : out std_logic; -- clk
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afi_addr : in std_logic_vector(19 downto 0) := (others => 'X'); -- afi_addr
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afi_ba : in std_logic_vector(2 downto 0) := (others => 'X'); -- afi_ba
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afi_cke : in std_logic_vector(1 downto 0) := (others => 'X'); -- afi_cke
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afi_cs_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- afi_cs_n
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afi_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_ras_n
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afi_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_we_n
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afi_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_cas_n
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afi_rst_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rst_n
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afi_odt : in std_logic_vector(1 downto 0) := (others => 'X'); -- afi_odt
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afi_dqs_burst : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_dqs_burst
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afi_wdata_valid : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_wdata_valid
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afi_wdata : in std_logic_vector(79 downto 0) := (others => 'X'); -- afi_wdata
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afi_dm : in std_logic_vector(9 downto 0) := (others => 'X'); -- afi_dm
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afi_rdata : out std_logic_vector(79 downto 0); -- afi_rdata
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afi_rdata_en : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_rdata_en
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afi_rdata_en_full : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_rdata_en_full
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afi_rdata_valid : out std_logic_vector(0 downto 0); -- afi_rdata_valid
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afi_wlat : out std_logic_vector(3 downto 0); -- afi_wlat
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afi_rlat : out std_logic_vector(4 downto 0); -- afi_rlat
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afi_cal_success : out std_logic; -- afi_cal_success
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afi_cal_fail : out std_logic; -- afi_cal_fail
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scc_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- scc_data
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scc_dqs_ena : in std_logic_vector(1 downto 0) := (others => 'X'); -- scc_dqs_ena
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scc_dqs_io_ena : in std_logic_vector(1 downto 0) := (others => 'X'); -- scc_dqs_io_ena
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scc_dq_ena : in std_logic_vector(15 downto 0) := (others => 'X'); -- scc_dq_ena
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scc_dm_ena : in std_logic_vector(1 downto 0) := (others => 'X'); -- scc_dm_ena
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capture_strobe_tracking : out std_logic_vector(1 downto 0); -- capture_strobe_tracking
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scc_upd : in std_logic_vector(0 downto 0) := (others => 'X'); -- scc_upd
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cfg_addlat : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_addlat
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cfg_bankaddrwidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_bankaddrwidth
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cfg_caswrlat : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_caswrlat
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cfg_coladdrwidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_coladdrwidth
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cfg_csaddrwidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_csaddrwidth
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cfg_devicewidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_devicewidth
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cfg_dramconfig : in std_logic_vector(23 downto 0) := (others => 'X'); -- cfg_dramconfig
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cfg_interfacewidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_interfacewidth
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cfg_rowaddrwidth : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_rowaddrwidth
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cfg_tcl : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_tcl
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cfg_tmrd : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_tmrd
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cfg_trefi : in std_logic_vector(15 downto 0) := (others => 'X'); -- cfg_trefi
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cfg_trfc : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_trfc
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cfg_twr : in std_logic_vector(7 downto 0) := (others => 'X'); -- cfg_twr
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afi_mem_clk_disable : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_mem_clk_disable
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pll_mem_clk : in std_logic := 'X'; -- pll_mem_clk
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pll_write_clk : in std_logic := 'X'; -- pll_write_clk
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pll_locked : in std_logic := 'X'; -- pll_locked
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pll_write_clk_pre_phy_clk : in std_logic := 'X'; -- pll_write_clk_pre_phy_clk
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pll_addr_cmd_clk : in std_logic := 'X'; -- pll_addr_cmd_clk
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pll_avl_clk : in std_logic := 'X'; -- pll_avl_clk
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pll_config_clk : in std_logic := 'X'; -- pll_config_clk
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pll_mem_phy_clk : in std_logic := 'X'; -- pll_mem_phy_clk
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afi_phy_clk : in std_logic := 'X'; -- afi_phy_clk
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pll_avl_phy_clk : in std_logic := 'X'; -- pll_avl_phy_clk
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dll_pll_locked : out std_logic; -- dll_pll_locked
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dll_delayctrl : in std_logic_vector(6 downto 0) := (others => 'X'); -- dll_delayctrl
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seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => 'X'); -- seriesterminationcontrol
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parallelterminationcontrol : in std_logic_vector(15 downto 0) := (others => 'X'); -- parallelterminationcontrol
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mem_a : out std_logic_vector(12 downto 0); -- mem_a
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mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
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mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
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mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
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mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
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mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
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mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
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mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
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mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
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mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
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mem_reset_n : out std_logic; -- mem_reset_n
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mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
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mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
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mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
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mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
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csr_clk : in std_logic := 'X'; -- clk
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csr_reset_n : in std_logic := 'X'; -- reset_n
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csr_write_req : in std_logic := 'X'; -- write
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csr_read_req : in std_logic := 'X'; -- read
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csr_waitrequest : out std_logic; -- waitrequest
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csr_addr : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
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csr_be : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
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csr_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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csr_rdata : out std_logic_vector(31 downto 0); -- readdata
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csr_rdata_valid : out std_logic; -- readdatavalid
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io_intaficalfail : out std_logic; -- io_intaficalfail
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io_intaficalsuccess : out std_logic; -- io_intaficalsuccess
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io_intaddrdout : in std_logic_vector(63 downto 0) := (others => 'X'); -- io_intaddrdout
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io_intbadout : in std_logic_vector(11 downto 0) := (others => 'X'); -- io_intbadout
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io_intcasndout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intcasndout
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io_intckdout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intckdout
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io_intckedout : in std_logic_vector(7 downto 0) := (others => 'X'); -- io_intckedout
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io_intckndout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intckndout
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io_intcsndout : in std_logic_vector(7 downto 0) := (others => 'X'); -- io_intcsndout
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io_intdmdout : in std_logic_vector(19 downto 0) := (others => 'X'); -- io_intdmdout
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io_intdqdin : out std_logic_vector(179 downto 0); -- io_intdqdin
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io_intdqdout : in std_logic_vector(179 downto 0) := (others => 'X'); -- io_intdqdout
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io_intdqoe : in std_logic_vector(89 downto 0) := (others => 'X'); -- io_intdqoe
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io_intdqsbdout : in std_logic_vector(19 downto 0) := (others => 'X'); -- io_intdqsbdout
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io_intdqsboe : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqsboe
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io_intdqsdout : in std_logic_vector(19 downto 0) := (others => 'X'); -- io_intdqsdout
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io_intdqslogicdqsena : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqslogicdqsena
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io_intdqslogicfiforeset : in std_logic_vector(4 downto 0) := (others => 'X'); -- io_intdqslogicfiforeset
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io_intdqslogicincrdataen : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqslogicincrdataen
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io_intdqslogicincwrptr : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqslogicincwrptr
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io_intdqslogicoct : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqslogicoct
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io_intdqslogicrdatavalid : out std_logic_vector(4 downto 0); -- io_intdqslogicrdatavalid
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io_intdqslogicreadlatency : in std_logic_vector(24 downto 0) := (others => 'X'); -- io_intdqslogicreadlatency
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io_intdqsoe : in std_logic_vector(9 downto 0) := (others => 'X'); -- io_intdqsoe
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io_intodtdout : in std_logic_vector(7 downto 0) := (others => 'X'); -- io_intodtdout
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|
|
io_intrasndout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intrasndou
|
||
|
|
io_intresetndout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intresetndout
|
||
|
|
io_intwendout : in std_logic_vector(3 downto 0) := (others => 'X'); -- io_intwendout
|
||
|
|
io_intafirlat : out std_logic_vector(4 downto 0); -- io_intafirlat
|
||
|
|
io_intafiwlat : out std_logic_vector(3 downto 0) -- io_intafiwlat
|
||
|
|
);
|
||
|
|
end component ddr3_p0;
|
||
|
|
|
||
|
|
component ddr3_s0 is
|
||
|
|
port (
|
||
|
|
avl_clk : in std_logic := 'X'; -- clk
|
||
|
|
avl_reset_n : in std_logic := 'X'; -- reset_n
|
||
|
|
scc_clk : in std_logic := 'X'; -- clk
|
||
|
|
reset_n_scc_clk : in std_logic := 'X'; -- reset_n
|
||
|
|
scc_data : out std_logic_vector(0 downto 0); -- scc_data
|
||
|
|
scc_dqs_ena : out std_logic_vector(1 downto 0); -- scc_dqs_ena
|
||
|
|
scc_dqs_io_ena : out std_logic_vector(1 downto 0); -- scc_dqs_io_ena
|
||
|
|
scc_dq_ena : out std_logic_vector(15 downto 0); -- scc_dq_ena
|
||
|
|
scc_dm_ena : out std_logic_vector(1 downto 0); -- scc_dm_ena
|
||
|
|
capture_strobe_tracking : in std_logic_vector(1 downto 0) := (others => 'X'); -- capture_strobe_tracking
|
||
|
|
scc_upd : out std_logic_vector(0 downto 0); -- scc_upd
|
||
|
|
afi_init_req : in std_logic := 'X'; -- afi_init_req
|
||
|
|
afi_cal_req : in std_logic := 'X'; -- afi_cal_req
|
||
|
|
avl_address : out std_logic_vector(15 downto 0); -- address
|
||
|
|
avl_write : out std_logic; -- write
|
||
|
|
avl_writedata : out std_logic_vector(31 downto 0); -- writedata
|
||
|
|
avl_read : out std_logic; -- read
|
||
|
|
avl_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
|
||
|
|
avl_waitrequest : in std_logic := 'X'; -- waitrequest
|
||
|
|
seq_waitrequest : out std_logic; -- waitrequest
|
||
|
|
seq_readdata : out std_logic_vector(31 downto 0); -- readdata
|
||
|
|
seq_readdatavalid : out std_logic; -- readdatavalid
|
||
|
|
seq_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
|
||
|
|
seq_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
|
||
|
|
seq_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
|
||
|
|
seq_write : in std_logic := 'X'; -- write
|
||
|
|
seq_read : in std_logic := 'X'; -- read
|
||
|
|
seq_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
seq_debugaccess : in std_logic := 'X' -- debugaccess
|
||
|
|
);
|
||
|
|
end component ddr3_s0;
|
||
|
|
|
||
|
|
component ddr3_dmaster is
|
||
|
|
port (
|
||
|
|
clk_clk : in std_logic := 'X'; -- clk
|
||
|
|
clk_reset_reset : in std_logic := 'X'; -- reset
|
||
|
|
master_address : out std_logic_vector(31 downto 0); -- address
|
||
|
|
master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
|
||
|
|
master_read : out std_logic; -- read
|
||
|
|
master_write : out std_logic; -- write
|
||
|
|
master_writedata : out std_logic_vector(31 downto 0); -- writedata
|
||
|
|
master_waitrequest : in std_logic := 'X'; -- waitrequest
|
||
|
|
master_readdatavalid : in std_logic := 'X'; -- readdatavalid
|
||
|
|
master_byteenable : out std_logic_vector(3 downto 0); -- byteenable
|
||
|
|
master_reset_reset : out std_logic -- reset
|
||
|
|
);
|
||
|
|
end component ddr3_dmaster;
|
||
|
|
|
||
|
|
component altera_mem_if_hard_memory_controller_top_cyclonev is
|
||
|
|
generic (
|
||
|
|
MEM_IF_DQS_WIDTH : integer := 0;
|
||
|
|
MEM_IF_CS_WIDTH : integer := 0;
|
||
|
|
MEM_IF_CHIP_BITS : integer := -1;
|
||
|
|
MEM_IF_CLK_PAIR_COUNT : integer := 1;
|
||
|
|
CSR_ADDR_WIDTH : integer := 8;
|
||
|
|
CSR_DATA_WIDTH : integer := 32;
|
||
|
|
CSR_BE_WIDTH : integer := 4;
|
||
|
|
AVL_ADDR_WIDTH : integer := 0;
|
||
|
|
AVL_DATA_WIDTH : integer := 0;
|
||
|
|
AVL_SIZE_WIDTH : integer := 0;
|
||
|
|
AVL_DATA_WIDTH_PORT_0 : integer := 0;
|
||
|
|
AVL_ADDR_WIDTH_PORT_0 : integer := 0;
|
||
|
|
AVL_NUM_SYMBOLS_PORT_0 : integer := 2;
|
||
|
|
LSB_WFIFO_PORT_0 : integer := 5;
|
||
|
|
MSB_WFIFO_PORT_0 : integer := 5;
|
||
|
|
LSB_RFIFO_PORT_0 : integer := 5;
|
||
|
|
MSB_RFIFO_PORT_0 : integer := 5;
|
||
|
|
AVL_DATA_WIDTH_PORT_1 : integer := 0;
|
||
|
|
AVL_ADDR_WIDTH_PORT_1 : integer := 0;
|
||
|
|
AVL_NUM_SYMBOLS_PORT_1 : integer := 2;
|
||
|
|
LSB_WFIFO_PORT_1 : integer := 5;
|
||
|
|
MSB_WFIFO_PORT_1 : integer := 5;
|
||
|
|
LSB_RFIFO_PORT_1 : integer := 5;
|
||
|
|
MSB_RFIFO_PORT_1 : integer := 5;
|
||
|
|
AVL_DATA_WIDTH_PORT_2 : integer := 0;
|
||
|
|
AVL_ADDR_WIDTH_PORT_2 : integer := 0;
|
||
|
|
AVL_NUM_SYMBOLS_PORT_2 : integer := 2;
|
||
|
|
LSB_WFIFO_PORT_2 : integer := 5;
|
||
|
|
MSB_WFIFO_PORT_2 : integer := 5;
|
||
|
|
LSB_RFIFO_PORT_2 : integer := 5;
|
||
|
|
MSB_RFIFO_PORT_2 : integer := 5;
|
||
|
|
AVL_DATA_WIDTH_PORT_3 : integer := 0;
|
||
|
|
AVL_ADDR_WIDTH_PORT_3 : integer := 0;
|
||
|
|
AVL_NUM_SYMBOLS_PORT_3 : integer := 2;
|
||
|
|
LSB_WFIFO_PORT_3 : integer := 5;
|
||
|
|
MSB_WFIFO_PORT_3 : integer := 5;
|
||
|
|
LSB_RFIFO_PORT_3 : integer := 5;
|
||
|
|
MSB_RFIFO_PORT_3 : integer := 5;
|
||
|
|
AVL_DATA_WIDTH_PORT_4 : integer := 0;
|
||
|
|
AVL_ADDR_WIDTH_PORT_4 : integer := 0;
|
||
|
|
AVL_NUM_SYMBOLS_PORT_4 : integer := 2;
|
||
|
|
LSB_WFIFO_PORT_4 : integer := 5;
|
||
|
|
MSB_WFIFO_PORT_4 : integer := 5;
|
||
|
|
LSB_RFIFO_PORT_4 : integer := 5;
|
||
|
|
MSB_RFIFO_PORT_4 : integer := 5;
|
||
|
|
AVL_DATA_WIDTH_PORT_5 : integer := 0;
|
||
|
|
AVL_ADDR_WIDTH_PORT_5 : integer := 0;
|
||
|
|
AVL_NUM_SYMBOLS_PORT_5 : integer := 2;
|
||
|
|
LSB_WFIFO_PORT_5 : integer := 5;
|
||
|
|
MSB_WFIFO_PORT_5 : integer := 5;
|
||
|
|
LSB_RFIFO_PORT_5 : integer := 5;
|
||
|
|
MSB_RFIFO_PORT_5 : integer := 5;
|
||
|
|
ENUM_ATTR_COUNTER_ONE_RESET : string := "DISABLED";
|
||
|
|
ENUM_ATTR_COUNTER_ZERO_RESET : string := "DISABLED";
|
||
|
|
ENUM_ATTR_STATIC_CONFIG_VALID : string := "DISABLED";
|
||
|
|
ENUM_AUTO_PCH_ENABLE_0 : string := "DISABLED";
|
||
|
|
ENUM_AUTO_PCH_ENABLE_1 : string := "DISABLED";
|
||
|
|
ENUM_AUTO_PCH_ENABLE_2 : string := "DISABLED";
|
||
|
|
ENUM_AUTO_PCH_ENABLE_3 : string := "DISABLED";
|
||
|
|
ENUM_AUTO_PCH_ENABLE_4 : string := "DISABLED";
|
||
|
|
ENUM_AUTO_PCH_ENABLE_5 : string := "DISABLED";
|
||
|
|
ENUM_CAL_REQ : string := "DISABLED";
|
||
|
|
ENUM_CFG_BURST_LENGTH : string := "BL_8";
|
||
|
|
ENUM_CFG_INTERFACE_WIDTH : string := "DWIDTH_32";
|
||
|
|
ENUM_CFG_SELF_RFSH_EXIT_CYCLES : string := "";
|
||
|
|
ENUM_CFG_STARVE_LIMIT : string := "STARVE_LIMIT_32";
|
||
|
|
ENUM_CFG_TYPE : string := "DDR3";
|
||
|
|
ENUM_CLOCK_OFF_0 : string := "DISABLED";
|
||
|
|
ENUM_CLOCK_OFF_1 : string := "DISABLED";
|
||
|
|
ENUM_CLOCK_OFF_2 : string := "DISABLED";
|
||
|
|
ENUM_CLOCK_OFF_3 : string := "DISABLED";
|
||
|
|
ENUM_CLOCK_OFF_4 : string := "DISABLED";
|
||
|
|
ENUM_CLOCK_OFF_5 : string := "DISABLED";
|
||
|
|
ENUM_CLR_INTR : string := "NO_CLR_INTR";
|
||
|
|
ENUM_CMD_PORT_IN_USE_0 : string := "FALSE";
|
||
|
|
ENUM_CMD_PORT_IN_USE_1 : string := "FALSE";
|
||
|
|
ENUM_CMD_PORT_IN_USE_2 : string := "FALSE";
|
||
|
|
ENUM_CMD_PORT_IN_USE_3 : string := "FALSE";
|
||
|
|
ENUM_CMD_PORT_IN_USE_4 : string := "FALSE";
|
||
|
|
ENUM_CMD_PORT_IN_USE_5 : string := "FALSE";
|
||
|
|
ENUM_CPORT0_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_CPORT0_RFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT0_TYPE : string := "DISABLE";
|
||
|
|
ENUM_CPORT0_WFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT1_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_CPORT1_RFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT1_TYPE : string := "DISABLE";
|
||
|
|
ENUM_CPORT1_WFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT2_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_CPORT2_RFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT2_TYPE : string := "DISABLE";
|
||
|
|
ENUM_CPORT2_WFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT3_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_CPORT3_RFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT3_TYPE : string := "DISABLE";
|
||
|
|
ENUM_CPORT3_WFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT4_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_CPORT4_RFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT4_TYPE : string := "DISABLE";
|
||
|
|
ENUM_CPORT4_WFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT5_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_CPORT5_RFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CPORT5_TYPE : string := "DISABLE";
|
||
|
|
ENUM_CPORT5_WFIFO_MAP : string := "FIFO_0";
|
||
|
|
ENUM_CTL_ADDR_ORDER : string := "CHIP_BANK_ROW_COL";
|
||
|
|
ENUM_CTL_ECC_ENABLED : string := "CTL_ECC_DISABLED";
|
||
|
|
ENUM_CTL_ECC_RMW_ENABLED : string := "CTL_ECC_RMW_DISABLED";
|
||
|
|
ENUM_CTL_REGDIMM_ENABLED : string := "REGDIMM_DISABLED";
|
||
|
|
ENUM_CTL_USR_REFRESH : string := "CTL_USR_REFRESH_DISABLED";
|
||
|
|
ENUM_CTRL_WIDTH : string := "DATA_WIDTH_64_BIT";
|
||
|
|
ENUM_DELAY_BONDING : string := "BONDING_LATENCY_0";
|
||
|
|
ENUM_DFX_BYPASS_ENABLE : string := "DFX_BYPASS_DISABLED";
|
||
|
|
ENUM_DISABLE_MERGING : string := "MERGING_ENABLED";
|
||
|
|
ENUM_ECC_DQ_WIDTH : string := "ECC_DQ_WIDTH_0";
|
||
|
|
ENUM_ENABLE_ATPG : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_BONDING_0 : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_BONDING_1 : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_BONDING_2 : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_BONDING_3 : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_BONDING_4 : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_BONDING_5 : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_BONDING_WRAPBACK : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_DQS_TRACKING : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_ECC_CODE_OVERWRITES : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_FAST_EXIT_PPD : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_INTR : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_NO_DM : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_PIPELINEGLOBAL : string := "DISABLED";
|
||
|
|
ENUM_GANGED_ARF : string := "DISABLED";
|
||
|
|
ENUM_GEN_DBE : string := "GEN_DBE_DISABLED";
|
||
|
|
ENUM_GEN_SBE : string := "GEN_SBE_DISABLED";
|
||
|
|
ENUM_INC_SYNC : string := "FIFO_SET_2";
|
||
|
|
ENUM_LOCAL_IF_CS_WIDTH : string := "ADDR_WIDTH_2";
|
||
|
|
ENUM_MASK_CORR_DROPPED_INTR : string := "DISABLED";
|
||
|
|
ENUM_MASK_DBE_INTR : string := "DISABLED";
|
||
|
|
ENUM_MASK_SBE_INTR : string := "DISABLED";
|
||
|
|
ENUM_MEM_IF_AL : string := "AL_0";
|
||
|
|
ENUM_MEM_IF_BANKADDR_WIDTH : string := "ADDR_WIDTH_3";
|
||
|
|
ENUM_MEM_IF_BURSTLENGTH : string := "MEM_IF_BURSTLENGTH_8";
|
||
|
|
ENUM_MEM_IF_COLADDR_WIDTH : string := "ADDR_WIDTH_12";
|
||
|
|
ENUM_MEM_IF_CS_PER_RANK : string := "MEM_IF_CS_PER_RANK_1";
|
||
|
|
ENUM_MEM_IF_CS_WIDTH : string := "MEM_IF_CS_WIDTH_1";
|
||
|
|
ENUM_MEM_IF_DQ_PER_CHIP : string := "MEM_IF_DQ_PER_CHIP_8";
|
||
|
|
ENUM_MEM_IF_DQS_WIDTH : string := "DQS_WIDTH_4";
|
||
|
|
ENUM_MEM_IF_DWIDTH : string := "MEM_IF_DWIDTH_32";
|
||
|
|
ENUM_MEM_IF_MEMTYPE : string := "DDR3_SDRAM";
|
||
|
|
ENUM_MEM_IF_ROWADDR_WIDTH : string := "ADDR_WIDTH_16";
|
||
|
|
ENUM_MEM_IF_SPEEDBIN : string := "DDR3_1066_6_6_6";
|
||
|
|
ENUM_MEM_IF_TCCD : string := "TCCD_4";
|
||
|
|
ENUM_MEM_IF_TCL : string := "TCL_6";
|
||
|
|
ENUM_MEM_IF_TCWL : string := "TCWL_5";
|
||
|
|
ENUM_MEM_IF_TFAW : string := "TFAW_16";
|
||
|
|
ENUM_MEM_IF_TMRD : string := "";
|
||
|
|
ENUM_MEM_IF_TRAS : string := "TRAS_16";
|
||
|
|
ENUM_MEM_IF_TRC : string := "TRC_22";
|
||
|
|
ENUM_MEM_IF_TRCD : string := "TRCD_6";
|
||
|
|
ENUM_MEM_IF_TRP : string := "TRP_6";
|
||
|
|
ENUM_MEM_IF_TRRD : string := "TRRD_4";
|
||
|
|
ENUM_MEM_IF_TRTP : string := "TRTP_4";
|
||
|
|
ENUM_MEM_IF_TWR : string := "TWR_6";
|
||
|
|
ENUM_MEM_IF_TWTR : string := "TWTR_4";
|
||
|
|
ENUM_MMR_CFG_MEM_BL : string := "MP_BL_8";
|
||
|
|
ENUM_OUTPUT_REGD : string := "DISABLED";
|
||
|
|
ENUM_PDN_EXIT_CYCLES : string := "SLOW_EXIT";
|
||
|
|
ENUM_PORT0_WIDTH : string := "PORT_64_BIT";
|
||
|
|
ENUM_PORT1_WIDTH : string := "PORT_64_BIT";
|
||
|
|
ENUM_PORT2_WIDTH : string := "PORT_64_BIT";
|
||
|
|
ENUM_PORT3_WIDTH : string := "PORT_64_BIT";
|
||
|
|
ENUM_PORT4_WIDTH : string := "PORT_64_BIT";
|
||
|
|
ENUM_PORT5_WIDTH : string := "PORT_64_BIT";
|
||
|
|
ENUM_PRIORITY_0_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_0_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_0_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_0_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_0_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_0_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_1_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_1_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_1_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_1_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_1_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_1_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_2_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_2_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_2_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_2_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_2_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_2_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_3_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_3_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_3_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_3_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_3_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_3_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_4_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_4_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_4_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_4_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_4_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_4_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_5_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_5_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_5_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_5_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_5_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_5_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_6_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_6_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_6_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_6_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_6_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_6_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_7_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_7_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_7_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_7_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_7_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_PRIORITY_7_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_RCFG_USER_PRIORITY_0 : string := "PRIORITY_0";
|
||
|
|
ENUM_RCFG_USER_PRIORITY_1 : string := "PRIORITY_0";
|
||
|
|
ENUM_RCFG_USER_PRIORITY_2 : string := "PRIORITY_0";
|
||
|
|
ENUM_RCFG_USER_PRIORITY_3 : string := "PRIORITY_0";
|
||
|
|
ENUM_RCFG_USER_PRIORITY_4 : string := "PRIORITY_0";
|
||
|
|
ENUM_RCFG_USER_PRIORITY_5 : string := "PRIORITY_0";
|
||
|
|
ENUM_RD_DWIDTH_0 : string := "DWIDTH_0";
|
||
|
|
ENUM_RD_DWIDTH_1 : string := "DWIDTH_0";
|
||
|
|
ENUM_RD_DWIDTH_2 : string := "DWIDTH_0";
|
||
|
|
ENUM_RD_DWIDTH_3 : string := "DWIDTH_0";
|
||
|
|
ENUM_RD_DWIDTH_4 : string := "DWIDTH_0";
|
||
|
|
ENUM_RD_DWIDTH_5 : string := "DWIDTH_0";
|
||
|
|
ENUM_RD_FIFO_IN_USE_0 : string := "FALSE";
|
||
|
|
ENUM_RD_FIFO_IN_USE_1 : string := "FALSE";
|
||
|
|
ENUM_RD_FIFO_IN_USE_2 : string := "FALSE";
|
||
|
|
ENUM_RD_FIFO_IN_USE_3 : string := "FALSE";
|
||
|
|
ENUM_RD_PORT_INFO_0 : string := "USE_NO";
|
||
|
|
ENUM_RD_PORT_INFO_1 : string := "USE_NO";
|
||
|
|
ENUM_RD_PORT_INFO_2 : string := "USE_NO";
|
||
|
|
ENUM_RD_PORT_INFO_3 : string := "USE_NO";
|
||
|
|
ENUM_RD_PORT_INFO_4 : string := "USE_NO";
|
||
|
|
ENUM_RD_PORT_INFO_5 : string := "USE_NO";
|
||
|
|
ENUM_READ_ODT_CHIP : string := "ODT_DISABLED";
|
||
|
|
ENUM_REORDER_DATA : string := "DATA_REORDERING";
|
||
|
|
ENUM_RFIFO0_CPORT_MAP : string := "CMD_PORT_0";
|
||
|
|
ENUM_RFIFO1_CPORT_MAP : string := "CMD_PORT_0";
|
||
|
|
ENUM_RFIFO2_CPORT_MAP : string := "CMD_PORT_0";
|
||
|
|
ENUM_RFIFO3_CPORT_MAP : string := "CMD_PORT_0";
|
||
|
|
ENUM_SINGLE_READY_0 : string := "CONCATENATE_RDY";
|
||
|
|
ENUM_SINGLE_READY_1 : string := "CONCATENATE_RDY";
|
||
|
|
ENUM_SINGLE_READY_2 : string := "CONCATENATE_RDY";
|
||
|
|
ENUM_SINGLE_READY_3 : string := "CONCATENATE_RDY";
|
||
|
|
ENUM_STATIC_WEIGHT_0 : string := "WEIGHT_0";
|
||
|
|
ENUM_STATIC_WEIGHT_1 : string := "WEIGHT_0";
|
||
|
|
ENUM_STATIC_WEIGHT_2 : string := "WEIGHT_0";
|
||
|
|
ENUM_STATIC_WEIGHT_3 : string := "WEIGHT_0";
|
||
|
|
ENUM_STATIC_WEIGHT_4 : string := "WEIGHT_0";
|
||
|
|
ENUM_STATIC_WEIGHT_5 : string := "WEIGHT_0";
|
||
|
|
ENUM_SYNC_MODE_0 : string := "ASYNCHRONOUS";
|
||
|
|
ENUM_SYNC_MODE_1 : string := "ASYNCHRONOUS";
|
||
|
|
ENUM_SYNC_MODE_2 : string := "ASYNCHRONOUS";
|
||
|
|
ENUM_SYNC_MODE_3 : string := "ASYNCHRONOUS";
|
||
|
|
ENUM_SYNC_MODE_4 : string := "ASYNCHRONOUS";
|
||
|
|
ENUM_SYNC_MODE_5 : string := "ASYNCHRONOUS";
|
||
|
|
ENUM_TEST_MODE : string := "NORMAL_MODE";
|
||
|
|
ENUM_THLD_JAR1_0 : string := "THRESHOLD_32";
|
||
|
|
ENUM_THLD_JAR1_1 : string := "THRESHOLD_32";
|
||
|
|
ENUM_THLD_JAR1_2 : string := "THRESHOLD_32";
|
||
|
|
ENUM_THLD_JAR1_3 : string := "THRESHOLD_32";
|
||
|
|
ENUM_THLD_JAR1_4 : string := "THRESHOLD_32";
|
||
|
|
ENUM_THLD_JAR1_5 : string := "THRESHOLD_32";
|
||
|
|
ENUM_THLD_JAR2_0 : string := "THRESHOLD_16";
|
||
|
|
ENUM_THLD_JAR2_1 : string := "THRESHOLD_16";
|
||
|
|
ENUM_THLD_JAR2_2 : string := "THRESHOLD_16";
|
||
|
|
ENUM_THLD_JAR2_3 : string := "THRESHOLD_16";
|
||
|
|
ENUM_THLD_JAR2_4 : string := "THRESHOLD_16";
|
||
|
|
ENUM_THLD_JAR2_5 : string := "THRESHOLD_16";
|
||
|
|
ENUM_USE_ALMOST_EMPTY_0 : string := "EMPTY";
|
||
|
|
ENUM_USE_ALMOST_EMPTY_1 : string := "EMPTY";
|
||
|
|
ENUM_USE_ALMOST_EMPTY_2 : string := "EMPTY";
|
||
|
|
ENUM_USE_ALMOST_EMPTY_3 : string := "EMPTY";
|
||
|
|
ENUM_USER_ECC_EN : string := "DISABLE";
|
||
|
|
ENUM_USER_PRIORITY_0 : string := "PRIORITY_0";
|
||
|
|
ENUM_USER_PRIORITY_1 : string := "PRIORITY_0";
|
||
|
|
ENUM_USER_PRIORITY_2 : string := "PRIORITY_0";
|
||
|
|
ENUM_USER_PRIORITY_3 : string := "PRIORITY_0";
|
||
|
|
ENUM_USER_PRIORITY_4 : string := "PRIORITY_0";
|
||
|
|
ENUM_USER_PRIORITY_5 : string := "PRIORITY_0";
|
||
|
|
ENUM_WFIFO0_CPORT_MAP : string := "CMD_PORT_0";
|
||
|
|
ENUM_WFIFO0_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_WFIFO1_CPORT_MAP : string := "CMD_PORT_0";
|
||
|
|
ENUM_WFIFO1_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_WFIFO2_CPORT_MAP : string := "CMD_PORT_0";
|
||
|
|
ENUM_WFIFO2_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_WFIFO3_CPORT_MAP : string := "CMD_PORT_0";
|
||
|
|
ENUM_WFIFO3_RDY_ALMOST_FULL : string := "NOT_FULL";
|
||
|
|
ENUM_WR_DWIDTH_0 : string := "DWIDTH_0";
|
||
|
|
ENUM_WR_DWIDTH_1 : string := "DWIDTH_0";
|
||
|
|
ENUM_WR_DWIDTH_2 : string := "DWIDTH_0";
|
||
|
|
ENUM_WR_DWIDTH_3 : string := "DWIDTH_0";
|
||
|
|
ENUM_WR_DWIDTH_4 : string := "DWIDTH_0";
|
||
|
|
ENUM_WR_DWIDTH_5 : string := "DWIDTH_0";
|
||
|
|
ENUM_WR_FIFO_IN_USE_0 : string := "FALSE";
|
||
|
|
ENUM_WR_FIFO_IN_USE_1 : string := "FALSE";
|
||
|
|
ENUM_WR_FIFO_IN_USE_2 : string := "FALSE";
|
||
|
|
ENUM_WR_FIFO_IN_USE_3 : string := "FALSE";
|
||
|
|
ENUM_WR_PORT_INFO_0 : string := "USE_NO";
|
||
|
|
ENUM_WR_PORT_INFO_1 : string := "USE_NO";
|
||
|
|
ENUM_WR_PORT_INFO_2 : string := "USE_NO";
|
||
|
|
ENUM_WR_PORT_INFO_3 : string := "USE_NO";
|
||
|
|
ENUM_WR_PORT_INFO_4 : string := "USE_NO";
|
||
|
|
ENUM_WR_PORT_INFO_5 : string := "USE_NO";
|
||
|
|
ENUM_WRITE_ODT_CHIP : string := "ODT_DISABLED";
|
||
|
|
INTG_MEM_AUTO_PD_CYCLES : integer := 0;
|
||
|
|
INTG_CYC_TO_RLD_JARS_0 : integer := 1;
|
||
|
|
INTG_CYC_TO_RLD_JARS_1 : integer := 1;
|
||
|
|
INTG_CYC_TO_RLD_JARS_2 : integer := 1;
|
||
|
|
INTG_CYC_TO_RLD_JARS_3 : integer := 1;
|
||
|
|
INTG_CYC_TO_RLD_JARS_4 : integer := 1;
|
||
|
|
INTG_CYC_TO_RLD_JARS_5 : integer := 1;
|
||
|
|
INTG_EXTRA_CTL_CLK_ACT_TO_ACT : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_ACT_TO_PCH : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_ARF_PERIOD : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_ARF_TO_VALID : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_PCH_TO_VALID : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_PDN_PERIOD : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_PDN_TO_VALID : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_PCH : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_RD : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_WR : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_SRF_TO_VALID : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_PCH : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_RD : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_WR : integer := 0;
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP : integer := 0;
|
||
|
|
INTG_MEM_IF_TREFI : integer := 3120;
|
||
|
|
INTG_MEM_IF_TRFC : integer := 34;
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_0 : integer := 0;
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_1 : integer := 0;
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_2 : integer := 0;
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_3 : integer := 0;
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_4 : integer := 0;
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_5 : integer := 0;
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_6 : integer := 0;
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_7 : integer := 0;
|
||
|
|
INTG_SUM_WT_PRIORITY_0 : integer := 0;
|
||
|
|
INTG_SUM_WT_PRIORITY_1 : integer := 0;
|
||
|
|
INTG_SUM_WT_PRIORITY_2 : integer := 0;
|
||
|
|
INTG_SUM_WT_PRIORITY_3 : integer := 0;
|
||
|
|
INTG_SUM_WT_PRIORITY_4 : integer := 0;
|
||
|
|
INTG_SUM_WT_PRIORITY_5 : integer := 0;
|
||
|
|
INTG_SUM_WT_PRIORITY_6 : integer := 0;
|
||
|
|
INTG_SUM_WT_PRIORITY_7 : integer := 0;
|
||
|
|
INTG_POWER_SAVING_EXIT_CYCLES : integer := 5;
|
||
|
|
INTG_MEM_CLK_ENTRY_CYCLES : integer := 10;
|
||
|
|
ENUM_ENABLE_BURST_INTERRUPT : string := "DISABLED";
|
||
|
|
ENUM_ENABLE_BURST_TERMINATE : string := "DISABLED";
|
||
|
|
AFI_RATE_RATIO : integer := 0;
|
||
|
|
AFI_ADDR_WIDTH : integer := 0;
|
||
|
|
AFI_BANKADDR_WIDTH : integer := 0;
|
||
|
|
AFI_CONTROL_WIDTH : integer := 0;
|
||
|
|
AFI_CS_WIDTH : integer := 0;
|
||
|
|
AFI_DM_WIDTH : integer := 0;
|
||
|
|
AFI_DQ_WIDTH : integer := 0;
|
||
|
|
AFI_ODT_WIDTH : integer := 0;
|
||
|
|
AFI_WRITE_DQS_WIDTH : integer := 0;
|
||
|
|
AFI_RLAT_WIDTH : integer := 0;
|
||
|
|
AFI_WLAT_WIDTH : integer := 0;
|
||
|
|
HARD_PHY : boolean := false
|
||
|
|
);
|
||
|
|
port (
|
||
|
|
afi_clk : in std_logic := 'X'; -- clk
|
||
|
|
afi_reset_n : in std_logic := 'X'; -- reset_n
|
||
|
|
ctl_reset_n : in std_logic := 'X'; -- reset_n
|
||
|
|
afi_half_clk : in std_logic := 'X'; -- clk
|
||
|
|
ctl_clk : in std_logic := 'X'; -- clk
|
||
|
|
mp_cmd_clk_0 : in std_logic := 'X'; -- clk
|
||
|
|
mp_cmd_reset_n_0 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_rfifo_clk_0 : in std_logic := 'X'; -- clk
|
||
|
|
mp_rfifo_reset_n_0 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_wfifo_clk_0 : in std_logic := 'X'; -- clk
|
||
|
|
mp_wfifo_reset_n_0 : in std_logic := 'X'; -- reset_n
|
||
|
|
csr_clk : in std_logic := 'X'; -- clk
|
||
|
|
csr_reset_n : in std_logic := 'X'; -- reset_n
|
||
|
|
avl_ready_0 : out std_logic; -- waitrequest_n
|
||
|
|
avl_burstbegin_0 : in std_logic := 'X'; -- beginbursttransfer
|
||
|
|
avl_addr_0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
|
||
|
|
avl_rdata_valid_0 : out std_logic; -- readdatavalid
|
||
|
|
avl_rdata_0 : out std_logic_vector(31 downto 0); -- readdata
|
||
|
|
avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
|
||
|
|
avl_be_0 : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
avl_read_req_0 : in std_logic := 'X'; -- read
|
||
|
|
avl_write_req_0 : in std_logic := 'X'; -- write
|
||
|
|
avl_size_0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
|
||
|
|
local_init_done : out std_logic; -- local_init_done
|
||
|
|
local_cal_success : out std_logic; -- local_cal_success
|
||
|
|
local_cal_fail : out std_logic; -- local_cal_fail
|
||
|
|
csr_write_req : in std_logic := 'X'; -- write
|
||
|
|
csr_read_req : in std_logic := 'X'; -- read
|
||
|
|
csr_waitrequest : out std_logic; -- waitrequest
|
||
|
|
csr_addr : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
|
||
|
|
csr_be : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
csr_wdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
|
||
|
|
csr_rdata : out std_logic_vector(7 downto 0); -- readdata
|
||
|
|
csr_rdata_valid : out std_logic; -- readdatavalid
|
||
|
|
afi_addr : out std_logic_vector(19 downto 0); -- afi_addr
|
||
|
|
afi_ba : out std_logic_vector(2 downto 0); -- afi_ba
|
||
|
|
afi_cke : out std_logic_vector(1 downto 0); -- afi_cke
|
||
|
|
afi_cs_n : out std_logic_vector(1 downto 0); -- afi_cs_n
|
||
|
|
afi_ras_n : out std_logic_vector(0 downto 0); -- afi_ras_n
|
||
|
|
afi_we_n : out std_logic_vector(0 downto 0); -- afi_we_n
|
||
|
|
afi_cas_n : out std_logic_vector(0 downto 0); -- afi_cas_n
|
||
|
|
afi_rst_n : out std_logic_vector(0 downto 0); -- afi_rst_n
|
||
|
|
afi_odt : out std_logic_vector(1 downto 0); -- afi_odt
|
||
|
|
afi_mem_clk_disable : out std_logic_vector(0 downto 0); -- afi_mem_clk_disable
|
||
|
|
afi_init_req : out std_logic; -- afi_init_req
|
||
|
|
afi_cal_req : out std_logic; -- afi_cal_req
|
||
|
|
afi_dqs_burst : out std_logic_vector(4 downto 0); -- afi_dqs_burst
|
||
|
|
afi_wdata_valid : out std_logic_vector(4 downto 0); -- afi_wdata_valid
|
||
|
|
afi_wdata : out std_logic_vector(79 downto 0); -- afi_wdata
|
||
|
|
afi_dm : out std_logic_vector(9 downto 0); -- afi_dm
|
||
|
|
afi_rdata : in std_logic_vector(79 downto 0) := (others => 'X'); -- afi_rdata
|
||
|
|
afi_rdata_en : out std_logic_vector(4 downto 0); -- afi_rdata_en
|
||
|
|
afi_rdata_en_full : out std_logic_vector(4 downto 0); -- afi_rdata_en_full
|
||
|
|
afi_rdata_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_rdata_valid
|
||
|
|
afi_wlat : in std_logic_vector(3 downto 0) := (others => 'X'); -- afi_wlat
|
||
|
|
afi_rlat : in std_logic_vector(4 downto 0) := (others => 'X'); -- afi_rlat
|
||
|
|
afi_cal_success : in std_logic := 'X'; -- afi_cal_success
|
||
|
|
afi_cal_fail : in std_logic := 'X'; -- afi_cal_fail
|
||
|
|
cfg_addlat : out std_logic_vector(7 downto 0); -- cfg_addlat
|
||
|
|
cfg_bankaddrwidth : out std_logic_vector(7 downto 0); -- cfg_bankaddrwidth
|
||
|
|
cfg_caswrlat : out std_logic_vector(7 downto 0); -- cfg_caswrlat
|
||
|
|
cfg_coladdrwidth : out std_logic_vector(7 downto 0); -- cfg_coladdrwidth
|
||
|
|
cfg_csaddrwidth : out std_logic_vector(7 downto 0); -- cfg_csaddrwidth
|
||
|
|
cfg_devicewidth : out std_logic_vector(7 downto 0); -- cfg_devicewidth
|
||
|
|
cfg_dramconfig : out std_logic_vector(23 downto 0); -- cfg_dramconfig
|
||
|
|
cfg_interfacewidth : out std_logic_vector(7 downto 0); -- cfg_interfacewidth
|
||
|
|
cfg_rowaddrwidth : out std_logic_vector(7 downto 0); -- cfg_rowaddrwidth
|
||
|
|
cfg_tcl : out std_logic_vector(7 downto 0); -- cfg_tcl
|
||
|
|
cfg_tmrd : out std_logic_vector(7 downto 0); -- cfg_tmrd
|
||
|
|
cfg_trefi : out std_logic_vector(15 downto 0); -- cfg_trefi
|
||
|
|
cfg_trfc : out std_logic_vector(7 downto 0); -- cfg_trfc
|
||
|
|
cfg_twr : out std_logic_vector(7 downto 0); -- cfg_twr
|
||
|
|
io_intaficalfail : in std_logic := 'X'; -- io_intaficalfail
|
||
|
|
io_intaficalsuccess : in std_logic := 'X'; -- io_intaficalsuccess
|
||
|
|
mp_cmd_clk_1 : in std_logic := 'X'; -- clk
|
||
|
|
mp_cmd_reset_n_1 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_cmd_clk_2 : in std_logic := 'X'; -- clk
|
||
|
|
mp_cmd_reset_n_2 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_cmd_clk_3 : in std_logic := 'X'; -- clk
|
||
|
|
mp_cmd_reset_n_3 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_cmd_clk_4 : in std_logic := 'X'; -- clk
|
||
|
|
mp_cmd_reset_n_4 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_cmd_clk_5 : in std_logic := 'X'; -- clk
|
||
|
|
mp_cmd_reset_n_5 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_rfifo_clk_1 : in std_logic := 'X'; -- clk
|
||
|
|
mp_rfifo_reset_n_1 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_wfifo_clk_1 : in std_logic := 'X'; -- clk
|
||
|
|
mp_wfifo_reset_n_1 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_rfifo_clk_2 : in std_logic := 'X'; -- clk
|
||
|
|
mp_rfifo_reset_n_2 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_wfifo_clk_2 : in std_logic := 'X'; -- clk
|
||
|
|
mp_wfifo_reset_n_2 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_rfifo_clk_3 : in std_logic := 'X'; -- clk
|
||
|
|
mp_rfifo_reset_n_3 : in std_logic := 'X'; -- reset_n
|
||
|
|
mp_wfifo_clk_3 : in std_logic := 'X'; -- clk
|
||
|
|
mp_wfifo_reset_n_3 : in std_logic := 'X'; -- reset_n
|
||
|
|
avl_ready_1 : out std_logic; -- waitrequest_n
|
||
|
|
avl_burstbegin_1 : in std_logic := 'X'; -- beginbursttransfer
|
||
|
|
avl_addr_1 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
|
||
|
|
avl_rdata_valid_1 : out std_logic; -- readdatavalid
|
||
|
|
avl_rdata_1 : out std_logic_vector(0 downto 0); -- readdata
|
||
|
|
avl_wdata_1 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata
|
||
|
|
avl_be_1 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
avl_read_req_1 : in std_logic := 'X'; -- read
|
||
|
|
avl_write_req_1 : in std_logic := 'X'; -- write
|
||
|
|
avl_size_1 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
|
||
|
|
avl_ready_2 : out std_logic; -- waitrequest_n
|
||
|
|
avl_burstbegin_2 : in std_logic := 'X'; -- beginbursttransfer
|
||
|
|
avl_addr_2 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
|
||
|
|
avl_rdata_valid_2 : out std_logic; -- readdatavalid
|
||
|
|
avl_rdata_2 : out std_logic_vector(0 downto 0); -- readdata
|
||
|
|
avl_wdata_2 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata
|
||
|
|
avl_be_2 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
avl_read_req_2 : in std_logic := 'X'; -- read
|
||
|
|
avl_write_req_2 : in std_logic := 'X'; -- write
|
||
|
|
avl_size_2 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
|
||
|
|
avl_ready_3 : out std_logic; -- waitrequest_n
|
||
|
|
avl_burstbegin_3 : in std_logic := 'X'; -- beginbursttransfer
|
||
|
|
avl_addr_3 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
|
||
|
|
avl_rdata_valid_3 : out std_logic; -- readdatavalid
|
||
|
|
avl_rdata_3 : out std_logic_vector(0 downto 0); -- readdata
|
||
|
|
avl_wdata_3 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata
|
||
|
|
avl_be_3 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
avl_read_req_3 : in std_logic := 'X'; -- read
|
||
|
|
avl_write_req_3 : in std_logic := 'X'; -- write
|
||
|
|
avl_size_3 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
|
||
|
|
avl_ready_4 : out std_logic; -- waitrequest_n
|
||
|
|
avl_burstbegin_4 : in std_logic := 'X'; -- beginbursttransfer
|
||
|
|
avl_addr_4 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
|
||
|
|
avl_rdata_valid_4 : out std_logic; -- readdatavalid
|
||
|
|
avl_rdata_4 : out std_logic_vector(0 downto 0); -- readdata
|
||
|
|
avl_wdata_4 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata
|
||
|
|
avl_be_4 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
avl_read_req_4 : in std_logic := 'X'; -- read
|
||
|
|
avl_write_req_4 : in std_logic := 'X'; -- write
|
||
|
|
avl_size_4 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
|
||
|
|
avl_ready_5 : out std_logic; -- waitrequest_n
|
||
|
|
avl_burstbegin_5 : in std_logic := 'X'; -- beginbursttransfer
|
||
|
|
avl_addr_5 : in std_logic_vector(0 downto 0) := (others => 'X'); -- address
|
||
|
|
avl_rdata_valid_5 : out std_logic; -- readdatavalid
|
||
|
|
avl_rdata_5 : out std_logic_vector(0 downto 0); -- readdata
|
||
|
|
avl_wdata_5 : in std_logic_vector(0 downto 0) := (others => 'X'); -- writedata
|
||
|
|
avl_be_5 : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
avl_read_req_5 : in std_logic := 'X'; -- read
|
||
|
|
avl_write_req_5 : in std_logic := 'X'; -- write
|
||
|
|
avl_size_5 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
|
||
|
|
afi_seq_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- afi_seq_busy
|
||
|
|
afi_ctl_refresh_done : out std_logic_vector(0 downto 0); -- afi_ctl_refresh_done
|
||
|
|
afi_ctl_long_idle : out std_logic_vector(0 downto 0); -- afi_ctl_long_idle
|
||
|
|
local_multicast : in std_logic := 'X'; -- local_multicast
|
||
|
|
local_refresh_req : in std_logic := 'X'; -- local_refresh_req
|
||
|
|
local_refresh_chip : in std_logic_vector(0 downto 0) := (others => 'X'); -- local_refresh_chip
|
||
|
|
local_refresh_ack : out std_logic; -- local_refresh_ack
|
||
|
|
local_self_rfsh_req : in std_logic := 'X'; -- local_self_rfsh_req
|
||
|
|
local_self_rfsh_chip : in std_logic_vector(0 downto 0) := (others => 'X'); -- local_self_rfsh_chip
|
||
|
|
local_self_rfsh_ack : out std_logic; -- local_self_rfsh_ack
|
||
|
|
local_deep_powerdn_req : in std_logic := 'X'; -- local_deep_powerdn_req
|
||
|
|
local_deep_powerdn_chip : in std_logic_vector(0 downto 0) := (others => 'X'); -- local_deep_powerdn_chip
|
||
|
|
local_deep_powerdn_ack : out std_logic; -- local_deep_powerdn_ack
|
||
|
|
local_powerdn_ack : out std_logic; -- local_powerdn_ack
|
||
|
|
local_priority : in std_logic := 'X'; -- local_priority
|
||
|
|
bonding_in_1 : in std_logic_vector(3 downto 0) := (others => 'X'); -- bonding1
|
||
|
|
bonding_in_2 : in std_logic_vector(5 downto 0) := (others => 'X'); -- bonding2
|
||
|
|
bonding_in_3 : in std_logic_vector(5 downto 0) := (others => 'X'); -- bonding3
|
||
|
|
bonding_out_1 : out std_logic_vector(3 downto 0); -- bonding1
|
||
|
|
bonding_out_2 : out std_logic_vector(5 downto 0); -- bonding2
|
||
|
|
bonding_out_3 : out std_logic_vector(5 downto 0) -- bonding3
|
||
|
|
);
|
||
|
|
end component altera_mem_if_hard_memory_controller_top_cyclonev;
|
||
|
|
|
||
|
|
component altera_mem_if_oct_cyclonev is
|
||
|
|
generic (
|
||
|
|
OCT_TERM_CONTROL_WIDTH : integer := 14
|
||
|
|
);
|
||
|
|
port (
|
||
|
|
oct_rzqin : in std_logic := 'X'; -- rzqin
|
||
|
|
seriesterminationcontrol : out std_logic_vector(15 downto 0); -- seriesterminationcontrol
|
||
|
|
parallelterminationcontrol : out std_logic_vector(15 downto 0) -- parallelterminationcontrol
|
||
|
|
);
|
||
|
|
end component altera_mem_if_oct_cyclonev;
|
||
|
|
|
||
|
|
component altera_mem_if_dll_cyclonev is
|
||
|
|
generic (
|
||
|
|
DLL_DELAY_CTRL_WIDTH : integer := 6;
|
||
|
|
DLL_OFFSET_CTRL_WIDTH : integer := 6;
|
||
|
|
DELAY_BUFFER_MODE : string := "HIGH";
|
||
|
|
DELAY_CHAIN_LENGTH : integer := 8;
|
||
|
|
DLL_INPUT_FREQUENCY_PS_STR : string := ""
|
||
|
|
);
|
||
|
|
port (
|
||
|
|
clk : in std_logic := 'X'; -- clk
|
||
|
|
dll_pll_locked : in std_logic := 'X'; -- dll_pll_locked
|
||
|
|
dll_delayctrl : out std_logic_vector(6 downto 0) -- dll_delayctrl
|
||
|
|
);
|
||
|
|
end component altera_mem_if_dll_cyclonev;
|
||
|
|
|
||
|
|
component ddr3_mm_interconnect_1 is
|
||
|
|
port (
|
||
|
|
p0_avl_clk_clk : in std_logic := 'X'; -- clk
|
||
|
|
dmaster_clk_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
|
||
|
|
dmaster_master_translator_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
|
||
|
|
dmaster_master_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
|
||
|
|
dmaster_master_waitrequest : out std_logic; -- waitrequest
|
||
|
|
dmaster_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
dmaster_master_read : in std_logic := 'X'; -- read
|
||
|
|
dmaster_master_readdata : out std_logic_vector(31 downto 0); -- readdata
|
||
|
|
dmaster_master_readdatavalid : out std_logic; -- readdatavalid
|
||
|
|
dmaster_master_write : in std_logic := 'X'; -- write
|
||
|
|
dmaster_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
|
||
|
|
s0_seq_debug_address : out std_logic_vector(31 downto 0); -- address
|
||
|
|
s0_seq_debug_write : out std_logic; -- write
|
||
|
|
s0_seq_debug_read : out std_logic; -- read
|
||
|
|
s0_seq_debug_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
|
||
|
|
s0_seq_debug_writedata : out std_logic_vector(31 downto 0); -- writedata
|
||
|
|
s0_seq_debug_burstcount : out std_logic_vector(0 downto 0); -- burstcount
|
||
|
|
s0_seq_debug_byteenable : out std_logic_vector(3 downto 0); -- byteenable
|
||
|
|
s0_seq_debug_readdatavalid : in std_logic := 'X'; -- readdatavalid
|
||
|
|
s0_seq_debug_waitrequest : in std_logic := 'X' -- waitrequest
|
||
|
|
);
|
||
|
|
end component ddr3_mm_interconnect_1;
|
||
|
|
|
||
|
|
component ddr3_mm_interconnect_2 is
|
||
|
|
port (
|
||
|
|
csr_clk_out_clk_clk : in std_logic := 'X'; -- clk
|
||
|
|
if_csr_m0_clk_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
|
||
|
|
p0_csr_reset_n_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
|
||
|
|
if_csr_m0_master_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
|
||
|
|
if_csr_m0_master_waitrequest : out std_logic; -- waitrequest
|
||
|
|
if_csr_m0_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
|
||
|
|
if_csr_m0_master_read : in std_logic := 'X'; -- read
|
||
|
|
if_csr_m0_master_readdata : out std_logic_vector(31 downto 0); -- readdata
|
||
|
|
if_csr_m0_master_readdatavalid : out std_logic; -- readdatavalid
|
||
|
|
if_csr_m0_master_write : in std_logic := 'X'; -- write
|
||
|
|
if_csr_m0_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
|
||
|
|
c0_csr_address : out std_logic_vector(9 downto 0); -- address
|
||
|
|
c0_csr_write : out std_logic; -- write
|
||
|
|
c0_csr_read : out std_logic; -- read
|
||
|
|
c0_csr_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
|
||
|
|
c0_csr_writedata : out std_logic_vector(7 downto 0); -- writedata
|
||
|
|
c0_csr_byteenable : out std_logic_vector(0 downto 0); -- byteenable
|
||
|
|
c0_csr_readdatavalid : in std_logic := 'X'; -- readdatavalid
|
||
|
|
c0_csr_waitrequest : in std_logic := 'X'; -- waitrequest
|
||
|
|
p0_csr_address : out std_logic_vector(7 downto 0); -- address
|
||
|
|
p0_csr_write : out std_logic; -- write
|
||
|
|
p0_csr_read : out std_logic; -- read
|
||
|
|
p0_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
|
||
|
|
p0_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
|
||
|
|
p0_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
|
||
|
|
p0_csr_readdatavalid : in std_logic := 'X'; -- readdatavalid
|
||
|
|
p0_csr_waitrequest : in std_logic := 'X' -- waitrequest
|
||
|
|
);
|
||
|
|
end component ddr3_mm_interconnect_2;
|
||
|
|
|
||
|
|
component altera_reset_controller is
|
||
|
|
generic (
|
||
|
|
NUM_RESET_INPUTS : integer := 6;
|
||
|
|
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
|
||
|
|
SYNC_DEPTH : integer := 2;
|
||
|
|
RESET_REQUEST_PRESENT : integer := 0;
|
||
|
|
RESET_REQ_WAIT_TIME : integer := 1;
|
||
|
|
MIN_RST_ASSERTION_TIME : integer := 3;
|
||
|
|
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
|
||
|
|
USE_RESET_REQUEST_IN0 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN1 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN2 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN3 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN4 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN5 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN6 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN7 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN8 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN9 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN10 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN11 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN12 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN13 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN14 : integer := 0;
|
||
|
|
USE_RESET_REQUEST_IN15 : integer := 0;
|
||
|
|
ADAPT_RESET_REQUEST : integer := 0
|
||
|
|
);
|
||
|
|
port (
|
||
|
|
reset_in0 : in std_logic := 'X'; -- reset
|
||
|
|
clk : in std_logic := 'X'; -- clk
|
||
|
|
reset_out : out std_logic; -- reset
|
||
|
|
reset_req : out std_logic; -- reset_req
|
||
|
|
reset_req_in0 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in1 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in1 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in2 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in2 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in3 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in3 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in4 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in4 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in5 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in5 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in6 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in6 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in7 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in7 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in8 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in8 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in9 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in9 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in10 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in10 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in11 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in11 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in12 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in12 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in13 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in13 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in14 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in14 : in std_logic := 'X'; -- reset_req
|
||
|
|
reset_in15 : in std_logic := 'X'; -- reset
|
||
|
|
reset_req_in15 : in std_logic := 'X' -- reset_req
|
||
|
|
);
|
||
|
|
end component altera_reset_controller;
|
||
|
|
|
||
|
|
signal pll0_afi_clk_clk : std_logic; -- pll0:afi_clk -> [afi_clk, c0:afi_clk, p0:afi_clk]
|
||
|
|
signal pll0_afi_half_clk_clk : std_logic; -- pll0:afi_half_clk -> [afi_half_clk, c0:afi_half_clk, p0:afi_half_clk]
|
||
|
|
signal p0_afi_reset_reset : std_logic; -- p0:afi_reset_n -> [afi_reset_n, c0:afi_reset_n]
|
||
|
|
signal p0_afi_afi_rlat : std_logic_vector(4 downto 0); -- p0:afi_rlat -> c0:afi_rlat
|
||
|
|
signal p0_afi_afi_cal_success : std_logic; -- p0:afi_cal_success -> c0:afi_cal_success
|
||
|
|
signal p0_afi_afi_rdata : std_logic_vector(79 downto 0); -- p0:afi_rdata -> c0:afi_rdata
|
||
|
|
signal p0_afi_afi_wlat : std_logic_vector(3 downto 0); -- p0:afi_wlat -> c0:afi_wlat
|
||
|
|
signal p0_afi_afi_cal_fail : std_logic; -- p0:afi_cal_fail -> c0:afi_cal_fail
|
||
|
|
signal p0_afi_afi_rdata_valid : std_logic_vector(0 downto 0); -- p0:afi_rdata_valid -> c0:afi_rdata_valid
|
||
|
|
signal p0_avl_clk_clk : std_logic; -- p0:avl_clk -> [dmaster:clk_clk, mm_interconnect_1:p0_avl_clk_clk, s0:avl_clk]
|
||
|
|
signal p0_avl_reset_reset : std_logic; -- p0:avl_reset_n -> [p0_avl_reset_reset:in, s0:avl_reset_n]
|
||
|
|
signal p0_scc_clk_clk : std_logic; -- p0:scc_clk -> s0:scc_clk
|
||
|
|
signal p0_scc_reset_reset : std_logic; -- p0:scc_reset_n -> s0:reset_n_scc_clk
|
||
|
|
signal s0_scc_scc_dq_ena : std_logic_vector(15 downto 0); -- s0:scc_dq_ena -> p0:scc_dq_ena
|
||
|
|
signal s0_scc_scc_upd : std_logic_vector(0 downto 0); -- s0:scc_upd -> p0:scc_upd
|
||
|
|
signal s0_scc_scc_dqs_io_ena : std_logic_vector(1 downto 0); -- s0:scc_dqs_io_ena -> p0:scc_dqs_io_ena
|
||
|
|
signal s0_scc_scc_dm_ena : std_logic_vector(1 downto 0); -- s0:scc_dm_ena -> p0:scc_dm_ena
|
||
|
|
signal p0_scc_capture_strobe_tracking : std_logic_vector(1 downto 0); -- p0:capture_strobe_tracking -> s0:capture_strobe_tracking
|
||
|
|
signal s0_scc_scc_dqs_ena : std_logic_vector(1 downto 0); -- s0:scc_dqs_ena -> p0:scc_dqs_ena
|
||
|
|
signal s0_scc_scc_data : std_logic_vector(0 downto 0); -- s0:scc_data -> p0:scc_data
|
||
|
|
signal s0_avl_readdata : std_logic_vector(31 downto 0); -- p0:avl_readdata -> s0:avl_readdata
|
||
|
|
signal s0_avl_waitrequest : std_logic; -- p0:avl_waitrequest -> s0:avl_waitrequest
|
||
|
|
signal s0_avl_address : std_logic_vector(15 downto 0); -- s0:avl_address -> p0:avl_address
|
||
|
|
signal s0_avl_read : std_logic; -- s0:avl_read -> p0:avl_read
|
||
|
|
signal s0_avl_write : std_logic; -- s0:avl_write -> p0:avl_write
|
||
|
|
signal s0_avl_writedata : std_logic_vector(31 downto 0); -- s0:avl_writedata -> p0:avl_writedata
|
||
|
|
signal dmaster_master_reset_reset : std_logic; -- dmaster:master_reset_reset -> p0:csr_soft_reset_req
|
||
|
|
signal c0_afi_afi_rdata_en_full : std_logic_vector(4 downto 0); -- c0:afi_rdata_en_full -> p0:afi_rdata_en_full
|
||
|
|
signal c0_afi_afi_wdata_valid : std_logic_vector(4 downto 0); -- c0:afi_wdata_valid -> p0:afi_wdata_valid
|
||
|
|
signal c0_afi_afi_rst_n : std_logic_vector(0 downto 0); -- c0:afi_rst_n -> p0:afi_rst_n
|
||
|
|
signal c0_afi_afi_wdata : std_logic_vector(79 downto 0); -- c0:afi_wdata -> p0:afi_wdata
|
||
|
|
signal c0_afi_afi_cal_req : std_logic; -- c0:afi_cal_req -> s0:afi_cal_req
|
||
|
|
signal c0_afi_afi_dqs_burst : std_logic_vector(4 downto 0); -- c0:afi_dqs_burst -> p0:afi_dqs_burst
|
||
|
|
signal c0_afi_afi_addr : std_logic_vector(19 downto 0); -- c0:afi_addr -> p0:afi_addr
|
||
|
|
signal c0_afi_afi_ba : std_logic_vector(2 downto 0); -- c0:afi_ba -> p0:afi_ba
|
||
|
|
signal c0_afi_afi_dm : std_logic_vector(9 downto 0); -- c0:afi_dm -> p0:afi_dm
|
||
|
|
signal c0_afi_afi_mem_clk_disable : std_logic_vector(0 downto 0); -- c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
|
||
|
|
signal c0_afi_afi_init_req : std_logic; -- c0:afi_init_req -> s0:afi_init_req
|
||
|
|
signal c0_afi_afi_we_n : std_logic_vector(0 downto 0); -- c0:afi_we_n -> p0:afi_we_n
|
||
|
|
signal c0_afi_afi_cas_n : std_logic_vector(0 downto 0); -- c0:afi_cas_n -> p0:afi_cas_n
|
||
|
|
signal c0_afi_afi_cs_n : std_logic_vector(1 downto 0); -- c0:afi_cs_n -> p0:afi_cs_n
|
||
|
|
signal c0_afi_afi_rdata_en : std_logic_vector(4 downto 0); -- c0:afi_rdata_en -> p0:afi_rdata_en
|
||
|
|
signal c0_afi_afi_odt : std_logic_vector(1 downto 0); -- c0:afi_odt -> p0:afi_odt
|
||
|
|
signal c0_afi_afi_ras_n : std_logic_vector(0 downto 0); -- c0:afi_ras_n -> p0:afi_ras_n
|
||
|
|
signal c0_afi_afi_cke : std_logic_vector(1 downto 0); -- c0:afi_cke -> p0:afi_cke
|
||
|
|
signal c0_hard_phy_cfg_cfg_tmrd : std_logic_vector(7 downto 0); -- c0:cfg_tmrd -> p0:cfg_tmrd
|
||
|
|
signal c0_hard_phy_cfg_cfg_dramconfig : std_logic_vector(23 downto 0); -- c0:cfg_dramconfig -> p0:cfg_dramconfig
|
||
|
|
signal c0_hard_phy_cfg_cfg_rowaddrwidth : std_logic_vector(7 downto 0); -- c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
|
||
|
|
signal c0_hard_phy_cfg_cfg_devicewidth : std_logic_vector(7 downto 0); -- c0:cfg_devicewidth -> p0:cfg_devicewidth
|
||
|
|
signal c0_hard_phy_cfg_cfg_trefi : std_logic_vector(15 downto 0); -- c0:cfg_trefi -> p0:cfg_trefi
|
||
|
|
signal c0_hard_phy_cfg_cfg_tcl : std_logic_vector(7 downto 0); -- c0:cfg_tcl -> p0:cfg_tcl
|
||
|
|
signal c0_hard_phy_cfg_cfg_csaddrwidth : std_logic_vector(7 downto 0); -- c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
|
||
|
|
signal c0_hard_phy_cfg_cfg_coladdrwidth : std_logic_vector(7 downto 0); -- c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
|
||
|
|
signal c0_hard_phy_cfg_cfg_trfc : std_logic_vector(7 downto 0); -- c0:cfg_trfc -> p0:cfg_trfc
|
||
|
|
signal c0_hard_phy_cfg_cfg_addlat : std_logic_vector(7 downto 0); -- c0:cfg_addlat -> p0:cfg_addlat
|
||
|
|
signal c0_hard_phy_cfg_cfg_bankaddrwidth : std_logic_vector(7 downto 0); -- c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
|
||
|
|
signal c0_hard_phy_cfg_cfg_interfacewidth : std_logic_vector(7 downto 0); -- c0:cfg_interfacewidth -> p0:cfg_interfacewidth
|
||
|
|
signal c0_hard_phy_cfg_cfg_twr : std_logic_vector(7 downto 0); -- c0:cfg_twr -> p0:cfg_twr
|
||
|
|
signal c0_hard_phy_cfg_cfg_caswrlat : std_logic_vector(7 downto 0); -- c0:cfg_caswrlat -> p0:cfg_caswrlat
|
||
|
|
signal p0_ctl_clk_clk : std_logic; -- p0:ctl_clk -> c0:ctl_clk
|
||
|
|
signal p0_ctl_reset_reset : std_logic; -- p0:ctl_reset_n -> c0:ctl_reset_n
|
||
|
|
signal p0_io_int_io_intaficalfail : std_logic; -- p0:io_intaficalfail -> c0:io_intaficalfail
|
||
|
|
signal p0_io_int_io_intaficalsuccess : std_logic; -- p0:io_intaficalsuccess -> c0:io_intaficalsuccess
|
||
|
|
signal oct0_oct_sharing_parallelterminationcontrol : std_logic_vector(15 downto 0); -- oct0:parallelterminationcontrol -> p0:parallelterminationcontrol
|
||
|
|
signal oct0_oct_sharing_seriesterminationcontrol : std_logic_vector(15 downto 0); -- oct0:seriesterminationcontrol -> p0:seriesterminationcontrol
|
||
|
|
signal pll0_pll_sharing_pll_write_clk : std_logic; -- pll0:pll_write_clk -> [pll_write_clk, p0:pll_write_clk]
|
||
|
|
signal pll0_pll_sharing_pll_avl_clk : std_logic; -- pll0:pll_avl_clk -> [pll_avl_clk, p0:pll_avl_clk]
|
||
|
|
signal pll0_pll_sharing_pll_write_clk_pre_phy_clk : std_logic; -- pll0:pll_write_clk_pre_phy_clk -> [pll_write_clk_pre_phy_clk, p0:pll_write_clk_pre_phy_clk]
|
||
|
|
signal pll0_pll_sharing_pll_addr_cmd_clk : std_logic; -- pll0:pll_addr_cmd_clk -> [pll_addr_cmd_clk, p0:pll_addr_cmd_clk]
|
||
|
|
signal pll0_pll_sharing_pll_config_clk : std_logic; -- pll0:pll_config_clk -> [pll_config_clk, p0:pll_config_clk]
|
||
|
|
signal pll0_pll_sharing_pll_avl_phy_clk : std_logic; -- pll0:pll_avl_phy_clk -> [pll_avl_phy_clk, p0:pll_avl_phy_clk]
|
||
|
|
signal pll0_pll_sharing_afi_phy_clk : std_logic; -- pll0:afi_phy_clk -> [afi_phy_clk, p0:afi_phy_clk]
|
||
|
|
signal pll0_pll_sharing_pll_mem_clk : std_logic; -- pll0:pll_mem_clk -> [pll_mem_clk, p0:pll_mem_clk]
|
||
|
|
signal pll0_pll_sharing_pll_locked : std_logic; -- pll0:pll_locked -> [pll_locked, p0:pll_locked]
|
||
|
|
signal pll0_pll_sharing_pll_mem_phy_clk : std_logic; -- pll0:pll_mem_phy_clk -> [pll_mem_phy_clk, p0:pll_mem_phy_clk]
|
||
|
|
signal p0_dll_clk_clk : std_logic; -- p0:dll_clk -> dll0:clk
|
||
|
|
signal p0_dll_sharing_dll_pll_locked : std_logic; -- p0:dll_pll_locked -> dll0:dll_pll_locked
|
||
|
|
signal dll0_dll_sharing_dll_delayctrl : std_logic_vector(6 downto 0); -- dll0:dll_delayctrl -> p0:dll_delayctrl
|
||
|
|
signal dmaster_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_1:dmaster_master_readdata -> dmaster:master_readdata
|
||
|
|
signal dmaster_master_waitrequest : std_logic; -- mm_interconnect_1:dmaster_master_waitrequest -> dmaster:master_waitrequest
|
||
|
|
signal dmaster_master_address : std_logic_vector(31 downto 0); -- dmaster:master_address -> mm_interconnect_1:dmaster_master_address
|
||
|
|
signal dmaster_master_read : std_logic; -- dmaster:master_read -> mm_interconnect_1:dmaster_master_read
|
||
|
|
signal dmaster_master_byteenable : std_logic_vector(3 downto 0); -- dmaster:master_byteenable -> mm_interconnect_1:dmaster_master_byteenable
|
||
|
|
signal dmaster_master_readdatavalid : std_logic; -- mm_interconnect_1:dmaster_master_readdatavalid -> dmaster:master_readdatavalid
|
||
|
|
signal dmaster_master_write : std_logic; -- dmaster:master_write -> mm_interconnect_1:dmaster_master_write
|
||
|
|
signal dmaster_master_writedata : std_logic_vector(31 downto 0); -- dmaster:master_writedata -> mm_interconnect_1:dmaster_master_writedata
|
||
|
|
signal mm_interconnect_1_s0_seq_debug_readdata : std_logic_vector(31 downto 0); -- s0:seq_readdata -> mm_interconnect_1:s0_seq_debug_readdata
|
||
|
|
signal mm_interconnect_1_s0_seq_debug_waitrequest : std_logic; -- s0:seq_waitrequest -> mm_interconnect_1:s0_seq_debug_waitrequest
|
||
|
|
signal mm_interconnect_1_s0_seq_debug_address : std_logic_vector(31 downto 0); -- mm_interconnect_1:s0_seq_debug_address -> s0:seq_address
|
||
|
|
signal mm_interconnect_1_s0_seq_debug_read : std_logic; -- mm_interconnect_1:s0_seq_debug_read -> s0:seq_read
|
||
|
|
signal mm_interconnect_1_s0_seq_debug_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_1:s0_seq_debug_byteenable -> s0:seq_byteenable
|
||
|
|
signal mm_interconnect_1_s0_seq_debug_readdatavalid : std_logic; -- s0:seq_readdatavalid -> mm_interconnect_1:s0_seq_debug_readdatavalid
|
||
|
|
signal mm_interconnect_1_s0_seq_debug_write : std_logic; -- mm_interconnect_1:s0_seq_debug_write -> s0:seq_write
|
||
|
|
signal mm_interconnect_1_s0_seq_debug_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_1:s0_seq_debug_writedata -> s0:seq_writedata
|
||
|
|
signal mm_interconnect_1_s0_seq_debug_burstcount : std_logic_vector(0 downto 0); -- mm_interconnect_1:s0_seq_debug_burstcount -> s0:seq_burstcount
|
||
|
|
signal if_csr_m0_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_2:if_csr_m0_master_readdata -> if_csr_m0:master_readdata
|
||
|
|
signal if_csr_m0_master_waitrequest : std_logic; -- mm_interconnect_2:if_csr_m0_master_waitrequest -> if_csr_m0:master_waitrequest
|
||
|
|
signal if_csr_m0_master_address : std_logic_vector(31 downto 0); -- if_csr_m0:master_address -> mm_interconnect_2:if_csr_m0_master_address
|
||
|
|
signal if_csr_m0_master_read : std_logic; -- if_csr_m0:master_read -> mm_interconnect_2:if_csr_m0_master_read
|
||
|
|
signal if_csr_m0_master_byteenable : std_logic_vector(3 downto 0); -- if_csr_m0:master_byteenable -> mm_interconnect_2:if_csr_m0_master_byteenable
|
||
|
|
signal if_csr_m0_master_readdatavalid : std_logic; -- mm_interconnect_2:if_csr_m0_master_readdatavalid -> if_csr_m0:master_readdatavalid
|
||
|
|
signal if_csr_m0_master_write : std_logic; -- if_csr_m0:master_write -> mm_interconnect_2:if_csr_m0_master_write
|
||
|
|
signal if_csr_m0_master_writedata : std_logic_vector(31 downto 0); -- if_csr_m0:master_writedata -> mm_interconnect_2:if_csr_m0_master_writedata
|
||
|
|
signal mm_interconnect_2_p0_csr_readdata : std_logic_vector(31 downto 0); -- p0:csr_rdata -> mm_interconnect_2:p0_csr_readdata
|
||
|
|
signal mm_interconnect_2_p0_csr_waitrequest : std_logic; -- p0:csr_waitrequest -> mm_interconnect_2:p0_csr_waitrequest
|
||
|
|
signal mm_interconnect_2_p0_csr_address : std_logic_vector(7 downto 0); -- mm_interconnect_2:p0_csr_address -> p0:csr_addr
|
||
|
|
signal mm_interconnect_2_p0_csr_read : std_logic; -- mm_interconnect_2:p0_csr_read -> p0:csr_read_req
|
||
|
|
signal mm_interconnect_2_p0_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_2:p0_csr_byteenable -> p0:csr_be
|
||
|
|
signal mm_interconnect_2_p0_csr_readdatavalid : std_logic; -- p0:csr_rdata_valid -> mm_interconnect_2:p0_csr_readdatavalid
|
||
|
|
signal mm_interconnect_2_p0_csr_write : std_logic; -- mm_interconnect_2:p0_csr_write -> p0:csr_write_req
|
||
|
|
signal mm_interconnect_2_p0_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_2:p0_csr_writedata -> p0:csr_wdata
|
||
|
|
signal mm_interconnect_2_c0_csr_readdata : std_logic_vector(7 downto 0); -- c0:csr_rdata -> mm_interconnect_2:c0_csr_readdata
|
||
|
|
signal mm_interconnect_2_c0_csr_waitrequest : std_logic; -- c0:csr_waitrequest -> mm_interconnect_2:c0_csr_waitrequest
|
||
|
|
signal mm_interconnect_2_c0_csr_address : std_logic_vector(9 downto 0); -- mm_interconnect_2:c0_csr_address -> c0:csr_addr
|
||
|
|
signal mm_interconnect_2_c0_csr_read : std_logic; -- mm_interconnect_2:c0_csr_read -> c0:csr_read_req
|
||
|
|
signal mm_interconnect_2_c0_csr_byteenable : std_logic_vector(0 downto 0); -- mm_interconnect_2:c0_csr_byteenable -> c0:csr_be
|
||
|
|
signal mm_interconnect_2_c0_csr_readdatavalid : std_logic; -- c0:csr_rdata_valid -> mm_interconnect_2:c0_csr_readdatavalid
|
||
|
|
signal mm_interconnect_2_c0_csr_write : std_logic; -- mm_interconnect_2:c0_csr_write -> c0:csr_write_req
|
||
|
|
signal mm_interconnect_2_c0_csr_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_2:c0_csr_writedata -> c0:csr_wdata
|
||
|
|
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [mm_interconnect_2:if_csr_m0_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_2:p0_csr_reset_n_reset_bridge_in_reset_reset, rst_controller_reset_out_reset:in]
|
||
|
|
signal csr_reset_n_ports_inv : std_logic; -- csr_reset_n:inv -> [if_csr_m0:clk_reset_reset, rst_controller:reset_in0]
|
||
|
|
signal p0_avl_reset_reset_ports_inv : std_logic; -- p0_avl_reset_reset:inv -> [dmaster:clk_reset_reset, mm_interconnect_1:dmaster_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:dmaster_master_translator_reset_reset_bridge_in_reset_reset]
|
||
|
|
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [c0:csr_reset_n, p0:csr_reset_n]
|
||
|
|
|
||
|
|
begin
|
||
|
|
|
||
|
|
pll0 : component ddr3_pll0
|
||
|
|
port map (
|
||
|
|
global_reset_n => global_reset_n, -- global_reset.reset_n
|
||
|
|
afi_clk => pll0_afi_clk_clk, -- afi_clk.clk
|
||
|
|
afi_half_clk => pll0_afi_half_clk_clk, -- afi_half_clk.clk
|
||
|
|
pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
|
||
|
|
pll_mem_clk => pll0_pll_sharing_pll_mem_clk, -- pll_sharing.pll_mem_clk
|
||
|
|
pll_write_clk => pll0_pll_sharing_pll_write_clk, -- .pll_write_clk
|
||
|
|
pll_locked => pll0_pll_sharing_pll_locked, -- .pll_locked
|
||
|
|
pll_write_clk_pre_phy_clk => pll0_pll_sharing_pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk
|
||
|
|
pll_addr_cmd_clk => pll0_pll_sharing_pll_addr_cmd_clk, -- .pll_addr_cmd_clk
|
||
|
|
pll_avl_clk => pll0_pll_sharing_pll_avl_clk, -- .pll_avl_clk
|
||
|
|
pll_config_clk => pll0_pll_sharing_pll_config_clk, -- .pll_config_clk
|
||
|
|
pll_mem_phy_clk => pll0_pll_sharing_pll_mem_phy_clk, -- .pll_mem_phy_clk
|
||
|
|
afi_phy_clk => pll0_pll_sharing_afi_phy_clk, -- .afi_phy_clk
|
||
|
|
pll_avl_phy_clk => pll0_pll_sharing_pll_avl_phy_clk -- .pll_avl_phy_clk
|
||
|
|
);
|
||
|
|
|
||
|
|
p0 : component ddr3_p0
|
||
|
|
port map (
|
||
|
|
global_reset_n => global_reset_n, -- global_reset.reset_n
|
||
|
|
soft_reset_n => soft_reset_n, -- soft_reset.reset_n
|
||
|
|
csr_soft_reset_req => dmaster_master_reset_reset, -- csr_soft_reset_req.reset
|
||
|
|
afi_reset_n => p0_afi_reset_reset, -- afi_reset.reset_n
|
||
|
|
afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
|
||
|
|
ctl_reset_n => p0_ctl_reset_reset, -- ctl_reset.reset_n
|
||
|
|
afi_clk => pll0_afi_clk_clk, -- afi_clk.clk
|
||
|
|
afi_half_clk => pll0_afi_half_clk_clk, -- afi_half_clk.clk
|
||
|
|
ctl_clk => p0_ctl_clk_clk, -- ctl_clk.clk
|
||
|
|
avl_clk => p0_avl_clk_clk, -- avl_clk.clk
|
||
|
|
avl_reset_n => p0_avl_reset_reset, -- avl_reset.reset_n
|
||
|
|
scc_clk => p0_scc_clk_clk, -- scc_clk.clk
|
||
|
|
scc_reset_n => p0_scc_reset_reset, -- scc_reset.reset_n
|
||
|
|
avl_address => s0_avl_address, -- avl.address
|
||
|
|
avl_write => s0_avl_write, -- .write
|
||
|
|
avl_writedata => s0_avl_writedata, -- .writedata
|
||
|
|
avl_read => s0_avl_read, -- .read
|
||
|
|
avl_readdata => s0_avl_readdata, -- .readdata
|
||
|
|
avl_waitrequest => s0_avl_waitrequest, -- .waitrequest
|
||
|
|
dll_clk => p0_dll_clk_clk, -- dll_clk.clk
|
||
|
|
afi_addr => c0_afi_afi_addr, -- afi.afi_addr
|
||
|
|
afi_ba => c0_afi_afi_ba, -- .afi_ba
|
||
|
|
afi_cke => c0_afi_afi_cke, -- .afi_cke
|
||
|
|
afi_cs_n => c0_afi_afi_cs_n, -- .afi_cs_n
|
||
|
|
afi_ras_n => c0_afi_afi_ras_n, -- .afi_ras_n
|
||
|
|
afi_we_n => c0_afi_afi_we_n, -- .afi_we_n
|
||
|
|
afi_cas_n => c0_afi_afi_cas_n, -- .afi_cas_n
|
||
|
|
afi_rst_n => c0_afi_afi_rst_n, -- .afi_rst_n
|
||
|
|
afi_odt => c0_afi_afi_odt, -- .afi_odt
|
||
|
|
afi_dqs_burst => c0_afi_afi_dqs_burst, -- .afi_dqs_burst
|
||
|
|
afi_wdata_valid => c0_afi_afi_wdata_valid, -- .afi_wdata_valid
|
||
|
|
afi_wdata => c0_afi_afi_wdata, -- .afi_wdata
|
||
|
|
afi_dm => c0_afi_afi_dm, -- .afi_dm
|
||
|
|
afi_rdata => p0_afi_afi_rdata, -- .afi_rdata
|
||
|
|
afi_rdata_en => c0_afi_afi_rdata_en, -- .afi_rdata_en
|
||
|
|
afi_rdata_en_full => c0_afi_afi_rdata_en_full, -- .afi_rdata_en_full
|
||
|
|
afi_rdata_valid => p0_afi_afi_rdata_valid, -- .afi_rdata_valid
|
||
|
|
afi_wlat => p0_afi_afi_wlat, -- .afi_wlat
|
||
|
|
afi_rlat => p0_afi_afi_rlat, -- .afi_rlat
|
||
|
|
afi_cal_success => p0_afi_afi_cal_success, -- .afi_cal_success
|
||
|
|
afi_cal_fail => p0_afi_afi_cal_fail, -- .afi_cal_fail
|
||
|
|
scc_data => s0_scc_scc_data, -- scc.scc_data
|
||
|
|
scc_dqs_ena => s0_scc_scc_dqs_ena, -- .scc_dqs_ena
|
||
|
|
scc_dqs_io_ena => s0_scc_scc_dqs_io_ena, -- .scc_dqs_io_ena
|
||
|
|
scc_dq_ena => s0_scc_scc_dq_ena, -- .scc_dq_ena
|
||
|
|
scc_dm_ena => s0_scc_scc_dm_ena, -- .scc_dm_ena
|
||
|
|
capture_strobe_tracking => p0_scc_capture_strobe_tracking, -- .capture_strobe_tracking
|
||
|
|
scc_upd => s0_scc_scc_upd, -- .scc_upd
|
||
|
|
cfg_addlat => c0_hard_phy_cfg_cfg_addlat, -- hard_phy_cfg.cfg_addlat
|
||
|
|
cfg_bankaddrwidth => c0_hard_phy_cfg_cfg_bankaddrwidth, -- .cfg_bankaddrwidth
|
||
|
|
cfg_caswrlat => c0_hard_phy_cfg_cfg_caswrlat, -- .cfg_caswrlat
|
||
|
|
cfg_coladdrwidth => c0_hard_phy_cfg_cfg_coladdrwidth, -- .cfg_coladdrwidth
|
||
|
|
cfg_csaddrwidth => c0_hard_phy_cfg_cfg_csaddrwidth, -- .cfg_csaddrwidth
|
||
|
|
cfg_devicewidth => c0_hard_phy_cfg_cfg_devicewidth, -- .cfg_devicewidth
|
||
|
|
cfg_dramconfig => c0_hard_phy_cfg_cfg_dramconfig, -- .cfg_dramconfig
|
||
|
|
cfg_interfacewidth => c0_hard_phy_cfg_cfg_interfacewidth, -- .cfg_interfacewidth
|
||
|
|
cfg_rowaddrwidth => c0_hard_phy_cfg_cfg_rowaddrwidth, -- .cfg_rowaddrwidth
|
||
|
|
cfg_tcl => c0_hard_phy_cfg_cfg_tcl, -- .cfg_tcl
|
||
|
|
cfg_tmrd => c0_hard_phy_cfg_cfg_tmrd, -- .cfg_tmrd
|
||
|
|
cfg_trefi => c0_hard_phy_cfg_cfg_trefi, -- .cfg_trefi
|
||
|
|
cfg_trfc => c0_hard_phy_cfg_cfg_trfc, -- .cfg_trfc
|
||
|
|
cfg_twr => c0_hard_phy_cfg_cfg_twr, -- .cfg_twr
|
||
|
|
afi_mem_clk_disable => c0_afi_afi_mem_clk_disable, -- afi_mem_clk_disable.afi_mem_clk_disable
|
||
|
|
pll_mem_clk => pll0_pll_sharing_pll_mem_clk, -- pll_sharing.pll_mem_clk
|
||
|
|
pll_write_clk => pll0_pll_sharing_pll_write_clk, -- .pll_write_clk
|
||
|
|
pll_locked => pll0_pll_sharing_pll_locked, -- .pll_locked
|
||
|
|
pll_write_clk_pre_phy_clk => pll0_pll_sharing_pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk
|
||
|
|
pll_addr_cmd_clk => pll0_pll_sharing_pll_addr_cmd_clk, -- .pll_addr_cmd_clk
|
||
|
|
pll_avl_clk => pll0_pll_sharing_pll_avl_clk, -- .pll_avl_clk
|
||
|
|
pll_config_clk => pll0_pll_sharing_pll_config_clk, -- .pll_config_clk
|
||
|
|
pll_mem_phy_clk => pll0_pll_sharing_pll_mem_phy_clk, -- .pll_mem_phy_clk
|
||
|
|
afi_phy_clk => pll0_pll_sharing_afi_phy_clk, -- .afi_phy_clk
|
||
|
|
pll_avl_phy_clk => pll0_pll_sharing_pll_avl_phy_clk, -- .pll_avl_phy_clk
|
||
|
|
dll_pll_locked => p0_dll_sharing_dll_pll_locked, -- dll_sharing.dll_pll_locked
|
||
|
|
dll_delayctrl => dll0_dll_sharing_dll_delayctrl, -- .dll_delayctrl
|
||
|
|
seriesterminationcontrol => oct0_oct_sharing_seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol
|
||
|
|
parallelterminationcontrol => oct0_oct_sharing_parallelterminationcontrol, -- .parallelterminationcontrol
|
||
|
|
mem_a => mem_a, -- memory.mem_a
|
||
|
|
mem_ba => mem_ba, -- .mem_ba
|
||
|
|
mem_ck => mem_ck, -- .mem_ck
|
||
|
|
mem_ck_n => mem_ck_n, -- .mem_ck_n
|
||
|
|
mem_cke => mem_cke, -- .mem_cke
|
||
|
|
mem_cs_n => mem_cs_n, -- .mem_cs_n
|
||
|
|
mem_dm => mem_dm, -- .mem_dm
|
||
|
|
mem_ras_n => mem_ras_n, -- .mem_ras_n
|
||
|
|
mem_cas_n => mem_cas_n, -- .mem_cas_n
|
||
|
|
mem_we_n => mem_we_n, -- .mem_we_n
|
||
|
|
mem_reset_n => mem_reset_n, -- .mem_reset_n
|
||
|
|
mem_dq => mem_dq, -- .mem_dq
|
||
|
|
mem_dqs => mem_dqs, -- .mem_dqs
|
||
|
|
mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
|
||
|
|
mem_odt => mem_odt, -- .mem_odt
|
||
|
|
csr_clk => csr_clk, -- csr_clk.clk
|
||
|
|
csr_reset_n => rst_controller_reset_out_reset_ports_inv, -- csr_reset_n.reset_n
|
||
|
|
csr_write_req => mm_interconnect_2_p0_csr_write, -- csr.write
|
||
|
|
csr_read_req => mm_interconnect_2_p0_csr_read, -- .read
|
||
|
|
csr_waitrequest => mm_interconnect_2_p0_csr_waitrequest, -- .waitrequest
|
||
|
|
csr_addr => mm_interconnect_2_p0_csr_address, -- .address
|
||
|
|
csr_be => mm_interconnect_2_p0_csr_byteenable, -- .byteenable
|
||
|
|
csr_wdata => mm_interconnect_2_p0_csr_writedata, -- .writedata
|
||
|
|
csr_rdata => mm_interconnect_2_p0_csr_readdata, -- .readdata
|
||
|
|
csr_rdata_valid => mm_interconnect_2_p0_csr_readdatavalid, -- .readdatavalid
|
||
|
|
io_intaficalfail => p0_io_int_io_intaficalfail, -- io_int.io_intaficalfail
|
||
|
|
io_intaficalsuccess => p0_io_int_io_intaficalsuccess, -- .io_intaficalsuccess
|
||
|
|
io_intaddrdout => "0000000000000000000000000000000000000000000000000000000000000000", -- (terminated)
|
||
|
|
io_intbadout => "000000000000", -- (terminated)
|
||
|
|
io_intcasndout => "0000", -- (terminated)
|
||
|
|
io_intckdout => "0000", -- (terminated)
|
||
|
|
io_intckedout => "00000000", -- (terminated)
|
||
|
|
io_intckndout => "0000", -- (terminated)
|
||
|
|
io_intcsndout => "00000000", -- (terminated)
|
||
|
|
io_intdmdout => "00000000000000000000", -- (terminated)
|
||
|
|
io_intdqdin => open, -- (terminated)
|
||
|
|
io_intdqdout => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", -- (terminated)
|
||
|
|
io_intdqoe => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", -- (terminated)
|
||
|
|
io_intdqsbdout => "00000000000000000000", -- (terminated)
|
||
|
|
io_intdqsboe => "0000000000", -- (terminated)
|
||
|
|
io_intdqsdout => "00000000000000000000", -- (terminated)
|
||
|
|
io_intdqslogicdqsena => "0000000000", -- (terminated)
|
||
|
|
io_intdqslogicfiforeset => "00000", -- (terminated)
|
||
|
|
io_intdqslogicincrdataen => "0000000000", -- (terminated)
|
||
|
|
io_intdqslogicincwrptr => "0000000000", -- (terminated)
|
||
|
|
io_intdqslogicoct => "0000000000", -- (terminated)
|
||
|
|
io_intdqslogicrdatavalid => open, -- (terminated)
|
||
|
|
io_intdqslogicreadlatency => "0000000000000000000000000", -- (terminated)
|
||
|
|
io_intdqsoe => "0000000000", -- (terminated)
|
||
|
|
io_intodtdout => "00000000", -- (terminated)
|
||
|
|
io_intrasndout => "0000", -- (terminated)
|
||
|
|
io_intresetndout => "0000", -- (terminated)
|
||
|
|
io_intwendout => "0000", -- (terminated)
|
||
|
|
io_intafirlat => open, -- (terminated)
|
||
|
|
io_intafiwlat => open -- (terminated)
|
||
|
|
);
|
||
|
|
|
||
|
|
s0 : component ddr3_s0
|
||
|
|
port map (
|
||
|
|
avl_clk => p0_avl_clk_clk, -- avl_clk.clk
|
||
|
|
avl_reset_n => p0_avl_reset_reset, -- avl_reset.reset_n
|
||
|
|
scc_clk => p0_scc_clk_clk, -- scc_clk.clk
|
||
|
|
reset_n_scc_clk => p0_scc_reset_reset, -- scc_reset.reset_n
|
||
|
|
scc_data => s0_scc_scc_data, -- scc.scc_data
|
||
|
|
scc_dqs_ena => s0_scc_scc_dqs_ena, -- .scc_dqs_ena
|
||
|
|
scc_dqs_io_ena => s0_scc_scc_dqs_io_ena, -- .scc_dqs_io_ena
|
||
|
|
scc_dq_ena => s0_scc_scc_dq_ena, -- .scc_dq_ena
|
||
|
|
scc_dm_ena => s0_scc_scc_dm_ena, -- .scc_dm_ena
|
||
|
|
capture_strobe_tracking => p0_scc_capture_strobe_tracking, -- .capture_strobe_tracking
|
||
|
|
scc_upd => s0_scc_scc_upd, -- .scc_upd
|
||
|
|
afi_init_req => c0_afi_afi_init_req, -- afi_init_cal_req.afi_init_req
|
||
|
|
afi_cal_req => c0_afi_afi_cal_req, -- .afi_cal_req
|
||
|
|
avl_address => s0_avl_address, -- avl.address
|
||
|
|
avl_write => s0_avl_write, -- .write
|
||
|
|
avl_writedata => s0_avl_writedata, -- .writedata
|
||
|
|
avl_read => s0_avl_read, -- .read
|
||
|
|
avl_readdata => s0_avl_readdata, -- .readdata
|
||
|
|
avl_waitrequest => s0_avl_waitrequest, -- .waitrequest
|
||
|
|
seq_waitrequest => mm_interconnect_1_s0_seq_debug_waitrequest, -- seq_debug.waitrequest
|
||
|
|
seq_readdata => mm_interconnect_1_s0_seq_debug_readdata, -- .readdata
|
||
|
|
seq_readdatavalid => mm_interconnect_1_s0_seq_debug_readdatavalid, -- .readdatavalid
|
||
|
|
seq_burstcount => mm_interconnect_1_s0_seq_debug_burstcount, -- .burstcount
|
||
|
|
seq_writedata => mm_interconnect_1_s0_seq_debug_writedata, -- .writedata
|
||
|
|
seq_address => mm_interconnect_1_s0_seq_debug_address, -- .address
|
||
|
|
seq_write => mm_interconnect_1_s0_seq_debug_write, -- .write
|
||
|
|
seq_read => mm_interconnect_1_s0_seq_debug_read, -- .read
|
||
|
|
seq_byteenable => mm_interconnect_1_s0_seq_debug_byteenable, -- .byteenable
|
||
|
|
seq_debugaccess => '0' -- (terminated)
|
||
|
|
);
|
||
|
|
|
||
|
|
dmaster : component ddr3_dmaster
|
||
|
|
port map (
|
||
|
|
clk_clk => p0_avl_clk_clk, -- clk.clk
|
||
|
|
clk_reset_reset => p0_avl_reset_reset_ports_inv, -- clk_reset.reset
|
||
|
|
master_address => dmaster_master_address, -- master.address
|
||
|
|
master_readdata => dmaster_master_readdata, -- .readdata
|
||
|
|
master_read => dmaster_master_read, -- .read
|
||
|
|
master_write => dmaster_master_write, -- .write
|
||
|
|
master_writedata => dmaster_master_writedata, -- .writedata
|
||
|
|
master_waitrequest => dmaster_master_waitrequest, -- .waitrequest
|
||
|
|
master_readdatavalid => dmaster_master_readdatavalid, -- .readdatavalid
|
||
|
|
master_byteenable => dmaster_master_byteenable, -- .byteenable
|
||
|
|
master_reset_reset => dmaster_master_reset_reset -- master_reset.reset
|
||
|
|
);
|
||
|
|
|
||
|
|
c0 : component altera_mem_if_hard_memory_controller_top_cyclonev
|
||
|
|
generic map (
|
||
|
|
MEM_IF_DQS_WIDTH => 2,
|
||
|
|
MEM_IF_CS_WIDTH => 1,
|
||
|
|
MEM_IF_CHIP_BITS => 1,
|
||
|
|
MEM_IF_CLK_PAIR_COUNT => 1,
|
||
|
|
CSR_ADDR_WIDTH => 10,
|
||
|
|
CSR_DATA_WIDTH => 8,
|
||
|
|
CSR_BE_WIDTH => 1,
|
||
|
|
AVL_ADDR_WIDTH => 25,
|
||
|
|
AVL_DATA_WIDTH => 32,
|
||
|
|
AVL_SIZE_WIDTH => 3,
|
||
|
|
AVL_DATA_WIDTH_PORT_0 => 32,
|
||
|
|
AVL_ADDR_WIDTH_PORT_0 => 25,
|
||
|
|
AVL_NUM_SYMBOLS_PORT_0 => 4,
|
||
|
|
LSB_WFIFO_PORT_0 => 0,
|
||
|
|
MSB_WFIFO_PORT_0 => 0,
|
||
|
|
LSB_RFIFO_PORT_0 => 0,
|
||
|
|
MSB_RFIFO_PORT_0 => 0,
|
||
|
|
AVL_DATA_WIDTH_PORT_1 => 1,
|
||
|
|
AVL_ADDR_WIDTH_PORT_1 => 1,
|
||
|
|
AVL_NUM_SYMBOLS_PORT_1 => 1,
|
||
|
|
LSB_WFIFO_PORT_1 => 5,
|
||
|
|
MSB_WFIFO_PORT_1 => 5,
|
||
|
|
LSB_RFIFO_PORT_1 => 5,
|
||
|
|
MSB_RFIFO_PORT_1 => 5,
|
||
|
|
AVL_DATA_WIDTH_PORT_2 => 1,
|
||
|
|
AVL_ADDR_WIDTH_PORT_2 => 1,
|
||
|
|
AVL_NUM_SYMBOLS_PORT_2 => 1,
|
||
|
|
LSB_WFIFO_PORT_2 => 5,
|
||
|
|
MSB_WFIFO_PORT_2 => 5,
|
||
|
|
LSB_RFIFO_PORT_2 => 5,
|
||
|
|
MSB_RFIFO_PORT_2 => 5,
|
||
|
|
AVL_DATA_WIDTH_PORT_3 => 1,
|
||
|
|
AVL_ADDR_WIDTH_PORT_3 => 1,
|
||
|
|
AVL_NUM_SYMBOLS_PORT_3 => 1,
|
||
|
|
LSB_WFIFO_PORT_3 => 5,
|
||
|
|
MSB_WFIFO_PORT_3 => 5,
|
||
|
|
LSB_RFIFO_PORT_3 => 5,
|
||
|
|
MSB_RFIFO_PORT_3 => 5,
|
||
|
|
AVL_DATA_WIDTH_PORT_4 => 1,
|
||
|
|
AVL_ADDR_WIDTH_PORT_4 => 1,
|
||
|
|
AVL_NUM_SYMBOLS_PORT_4 => 1,
|
||
|
|
LSB_WFIFO_PORT_4 => 5,
|
||
|
|
MSB_WFIFO_PORT_4 => 5,
|
||
|
|
LSB_RFIFO_PORT_4 => 5,
|
||
|
|
MSB_RFIFO_PORT_4 => 5,
|
||
|
|
AVL_DATA_WIDTH_PORT_5 => 1,
|
||
|
|
AVL_ADDR_WIDTH_PORT_5 => 1,
|
||
|
|
AVL_NUM_SYMBOLS_PORT_5 => 1,
|
||
|
|
LSB_WFIFO_PORT_5 => 5,
|
||
|
|
MSB_WFIFO_PORT_5 => 5,
|
||
|
|
LSB_RFIFO_PORT_5 => 5,
|
||
|
|
MSB_RFIFO_PORT_5 => 5,
|
||
|
|
ENUM_ATTR_COUNTER_ONE_RESET => "DISABLED",
|
||
|
|
ENUM_ATTR_COUNTER_ZERO_RESET => "DISABLED",
|
||
|
|
ENUM_ATTR_STATIC_CONFIG_VALID => "DISABLED",
|
||
|
|
ENUM_AUTO_PCH_ENABLE_0 => "DISABLED",
|
||
|
|
ENUM_AUTO_PCH_ENABLE_1 => "DISABLED",
|
||
|
|
ENUM_AUTO_PCH_ENABLE_2 => "DISABLED",
|
||
|
|
ENUM_AUTO_PCH_ENABLE_3 => "DISABLED",
|
||
|
|
ENUM_AUTO_PCH_ENABLE_4 => "DISABLED",
|
||
|
|
ENUM_AUTO_PCH_ENABLE_5 => "DISABLED",
|
||
|
|
ENUM_CAL_REQ => "DISABLED",
|
||
|
|
ENUM_CFG_BURST_LENGTH => "BL_8",
|
||
|
|
ENUM_CFG_INTERFACE_WIDTH => "DWIDTH_16",
|
||
|
|
ENUM_CFG_SELF_RFSH_EXIT_CYCLES => "SELF_RFSH_EXIT_CYCLES_512",
|
||
|
|
ENUM_CFG_STARVE_LIMIT => "STARVE_LIMIT_4",
|
||
|
|
ENUM_CFG_TYPE => "DDR3",
|
||
|
|
ENUM_CLOCK_OFF_0 => "DISABLED",
|
||
|
|
ENUM_CLOCK_OFF_1 => "DISABLED",
|
||
|
|
ENUM_CLOCK_OFF_2 => "DISABLED",
|
||
|
|
ENUM_CLOCK_OFF_3 => "DISABLED",
|
||
|
|
ENUM_CLOCK_OFF_4 => "DISABLED",
|
||
|
|
ENUM_CLOCK_OFF_5 => "DISABLED",
|
||
|
|
ENUM_CLR_INTR => "NO_CLR_INTR",
|
||
|
|
ENUM_CMD_PORT_IN_USE_0 => "TRUE",
|
||
|
|
ENUM_CMD_PORT_IN_USE_1 => "FALSE",
|
||
|
|
ENUM_CMD_PORT_IN_USE_2 => "FALSE",
|
||
|
|
ENUM_CMD_PORT_IN_USE_3 => "FALSE",
|
||
|
|
ENUM_CMD_PORT_IN_USE_4 => "FALSE",
|
||
|
|
ENUM_CMD_PORT_IN_USE_5 => "FALSE",
|
||
|
|
ENUM_CPORT0_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_CPORT0_RFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT0_TYPE => "BI_DIRECTION",
|
||
|
|
ENUM_CPORT0_WFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT1_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_CPORT1_RFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT1_TYPE => "DISABLE",
|
||
|
|
ENUM_CPORT1_WFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT2_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_CPORT2_RFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT2_TYPE => "DISABLE",
|
||
|
|
ENUM_CPORT2_WFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT3_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_CPORT3_RFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT3_TYPE => "DISABLE",
|
||
|
|
ENUM_CPORT3_WFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT4_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_CPORT4_RFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT4_TYPE => "DISABLE",
|
||
|
|
ENUM_CPORT4_WFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT5_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_CPORT5_RFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CPORT5_TYPE => "DISABLE",
|
||
|
|
ENUM_CPORT5_WFIFO_MAP => "FIFO_0",
|
||
|
|
ENUM_CTL_ADDR_ORDER => "CHIP_ROW_BANK_COL",
|
||
|
|
ENUM_CTL_ECC_ENABLED => "CTL_ECC_DISABLED",
|
||
|
|
ENUM_CTL_ECC_RMW_ENABLED => "CTL_ECC_RMW_DISABLED",
|
||
|
|
ENUM_CTL_REGDIMM_ENABLED => "REGDIMM_DISABLED",
|
||
|
|
ENUM_CTL_USR_REFRESH => "CTL_USR_REFRESH_DISABLED",
|
||
|
|
ENUM_CTRL_WIDTH => "DATA_WIDTH_32_BIT",
|
||
|
|
ENUM_DELAY_BONDING => "BONDING_LATENCY_0",
|
||
|
|
ENUM_DFX_BYPASS_ENABLE => "DFX_BYPASS_DISABLED",
|
||
|
|
ENUM_DISABLE_MERGING => "MERGING_ENABLED",
|
||
|
|
ENUM_ECC_DQ_WIDTH => "ECC_DQ_WIDTH_0",
|
||
|
|
ENUM_ENABLE_ATPG => "DISABLED",
|
||
|
|
ENUM_ENABLE_BONDING_0 => "DISABLED",
|
||
|
|
ENUM_ENABLE_BONDING_1 => "DISABLED",
|
||
|
|
ENUM_ENABLE_BONDING_2 => "DISABLED",
|
||
|
|
ENUM_ENABLE_BONDING_3 => "DISABLED",
|
||
|
|
ENUM_ENABLE_BONDING_4 => "DISABLED",
|
||
|
|
ENUM_ENABLE_BONDING_5 => "DISABLED",
|
||
|
|
ENUM_ENABLE_BONDING_WRAPBACK => "DISABLED",
|
||
|
|
ENUM_ENABLE_DQS_TRACKING => "DISABLED",
|
||
|
|
ENUM_ENABLE_ECC_CODE_OVERWRITES => "DISABLED",
|
||
|
|
ENUM_ENABLE_FAST_EXIT_PPD => "DISABLED",
|
||
|
|
ENUM_ENABLE_INTR => "DISABLED",
|
||
|
|
ENUM_ENABLE_NO_DM => "DISABLED",
|
||
|
|
ENUM_ENABLE_PIPELINEGLOBAL => "DISABLED",
|
||
|
|
ENUM_GANGED_ARF => "DISABLED",
|
||
|
|
ENUM_GEN_DBE => "GEN_DBE_DISABLED",
|
||
|
|
ENUM_GEN_SBE => "GEN_SBE_DISABLED",
|
||
|
|
ENUM_INC_SYNC => "FIFO_SET_2",
|
||
|
|
ENUM_LOCAL_IF_CS_WIDTH => "ADDR_WIDTH_0",
|
||
|
|
ENUM_MASK_CORR_DROPPED_INTR => "DISABLED",
|
||
|
|
ENUM_MASK_DBE_INTR => "DISABLED",
|
||
|
|
ENUM_MASK_SBE_INTR => "DISABLED",
|
||
|
|
ENUM_MEM_IF_AL => "AL_0",
|
||
|
|
ENUM_MEM_IF_BANKADDR_WIDTH => "ADDR_WIDTH_3",
|
||
|
|
ENUM_MEM_IF_BURSTLENGTH => "MEM_IF_BURSTLENGTH_8",
|
||
|
|
ENUM_MEM_IF_COLADDR_WIDTH => "ADDR_WIDTH_10",
|
||
|
|
ENUM_MEM_IF_CS_PER_RANK => "MEM_IF_CS_PER_RANK_1",
|
||
|
|
ENUM_MEM_IF_CS_WIDTH => "MEM_IF_CS_WIDTH_1",
|
||
|
|
ENUM_MEM_IF_DQ_PER_CHIP => "MEM_IF_DQ_PER_CHIP_8",
|
||
|
|
ENUM_MEM_IF_DQS_WIDTH => "DQS_WIDTH_2",
|
||
|
|
ENUM_MEM_IF_DWIDTH => "MEM_IF_DWIDTH_16",
|
||
|
|
ENUM_MEM_IF_MEMTYPE => "DDR3_SDRAM",
|
||
|
|
ENUM_MEM_IF_ROWADDR_WIDTH => "ADDR_WIDTH_13",
|
||
|
|
ENUM_MEM_IF_SPEEDBIN => "DDR3_1600_8_8_8",
|
||
|
|
ENUM_MEM_IF_TCCD => "TCCD_4",
|
||
|
|
ENUM_MEM_IF_TCL => "TCL_7",
|
||
|
|
ENUM_MEM_IF_TCWL => "TCWL_6",
|
||
|
|
ENUM_MEM_IF_TFAW => "TFAW_14",
|
||
|
|
ENUM_MEM_IF_TMRD => "TMRD_4",
|
||
|
|
ENUM_MEM_IF_TRAS => "TRAS_11",
|
||
|
|
ENUM_MEM_IF_TRC => "TRC_15",
|
||
|
|
ENUM_MEM_IF_TRCD => "TRCD_5",
|
||
|
|
ENUM_MEM_IF_TRP => "TRP_5",
|
||
|
|
ENUM_MEM_IF_TRRD => "TRRD_3",
|
||
|
|
ENUM_MEM_IF_TRTP => "TRTP_3",
|
||
|
|
ENUM_MEM_IF_TWR => "TWR_5",
|
||
|
|
ENUM_MEM_IF_TWTR => "TWTR_5",
|
||
|
|
ENUM_MMR_CFG_MEM_BL => "MP_BL_8",
|
||
|
|
ENUM_OUTPUT_REGD => "DISABLED",
|
||
|
|
ENUM_PDN_EXIT_CYCLES => "SLOW_EXIT",
|
||
|
|
ENUM_PORT0_WIDTH => "PORT_32_BIT",
|
||
|
|
ENUM_PORT1_WIDTH => "PORT_32_BIT",
|
||
|
|
ENUM_PORT2_WIDTH => "PORT_32_BIT",
|
||
|
|
ENUM_PORT3_WIDTH => "PORT_32_BIT",
|
||
|
|
ENUM_PORT4_WIDTH => "PORT_32_BIT",
|
||
|
|
ENUM_PORT5_WIDTH => "PORT_32_BIT",
|
||
|
|
ENUM_PRIORITY_0_0 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_0_1 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_0_2 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_0_3 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_0_4 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_0_5 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_1_0 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_1_1 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_1_2 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_1_3 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_1_4 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_1_5 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_2_0 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_2_1 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_2_2 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_2_3 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_2_4 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_2_5 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_3_0 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_3_1 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_3_2 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_3_3 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_3_4 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_3_5 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_4_0 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_4_1 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_4_2 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_4_3 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_4_4 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_4_5 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_5_0 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_5_1 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_5_2 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_5_3 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_5_4 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_5_5 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_6_0 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_6_1 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_6_2 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_6_3 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_6_4 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_6_5 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_7_0 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_7_1 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_7_2 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_7_3 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_7_4 => "WEIGHT_0",
|
||
|
|
ENUM_PRIORITY_7_5 => "WEIGHT_0",
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_0 => "WEIGHT_0",
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_1 => "WEIGHT_0",
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_2 => "WEIGHT_0",
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_3 => "WEIGHT_0",
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_4 => "WEIGHT_0",
|
||
|
|
ENUM_RCFG_STATIC_WEIGHT_5 => "WEIGHT_0",
|
||
|
|
ENUM_RCFG_USER_PRIORITY_0 => "PRIORITY_1",
|
||
|
|
ENUM_RCFG_USER_PRIORITY_1 => "PRIORITY_1",
|
||
|
|
ENUM_RCFG_USER_PRIORITY_2 => "PRIORITY_1",
|
||
|
|
ENUM_RCFG_USER_PRIORITY_3 => "PRIORITY_1",
|
||
|
|
ENUM_RCFG_USER_PRIORITY_4 => "PRIORITY_1",
|
||
|
|
ENUM_RCFG_USER_PRIORITY_5 => "PRIORITY_1",
|
||
|
|
ENUM_RD_DWIDTH_0 => "DWIDTH_32",
|
||
|
|
ENUM_RD_DWIDTH_1 => "DWIDTH_0",
|
||
|
|
ENUM_RD_DWIDTH_2 => "DWIDTH_0",
|
||
|
|
ENUM_RD_DWIDTH_3 => "DWIDTH_0",
|
||
|
|
ENUM_RD_DWIDTH_4 => "DWIDTH_0",
|
||
|
|
ENUM_RD_DWIDTH_5 => "DWIDTH_0",
|
||
|
|
ENUM_RD_FIFO_IN_USE_0 => "TRUE",
|
||
|
|
ENUM_RD_FIFO_IN_USE_1 => "FALSE",
|
||
|
|
ENUM_RD_FIFO_IN_USE_2 => "FALSE",
|
||
|
|
ENUM_RD_FIFO_IN_USE_3 => "FALSE",
|
||
|
|
ENUM_RD_PORT_INFO_0 => "USE_0",
|
||
|
|
ENUM_RD_PORT_INFO_1 => "USE_NO",
|
||
|
|
ENUM_RD_PORT_INFO_2 => "USE_NO",
|
||
|
|
ENUM_RD_PORT_INFO_3 => "USE_NO",
|
||
|
|
ENUM_RD_PORT_INFO_4 => "USE_NO",
|
||
|
|
ENUM_RD_PORT_INFO_5 => "USE_NO",
|
||
|
|
ENUM_READ_ODT_CHIP => "ODT_DISABLED",
|
||
|
|
ENUM_REORDER_DATA => "NO_DATA_REORDERING",
|
||
|
|
ENUM_RFIFO0_CPORT_MAP => "CMD_PORT_0",
|
||
|
|
ENUM_RFIFO1_CPORT_MAP => "CMD_PORT_0",
|
||
|
|
ENUM_RFIFO2_CPORT_MAP => "CMD_PORT_0",
|
||
|
|
ENUM_RFIFO3_CPORT_MAP => "CMD_PORT_0",
|
||
|
|
ENUM_SINGLE_READY_0 => "CONCATENATE_RDY",
|
||
|
|
ENUM_SINGLE_READY_1 => "CONCATENATE_RDY",
|
||
|
|
ENUM_SINGLE_READY_2 => "CONCATENATE_RDY",
|
||
|
|
ENUM_SINGLE_READY_3 => "CONCATENATE_RDY",
|
||
|
|
ENUM_STATIC_WEIGHT_0 => "WEIGHT_0",
|
||
|
|
ENUM_STATIC_WEIGHT_1 => "WEIGHT_0",
|
||
|
|
ENUM_STATIC_WEIGHT_2 => "WEIGHT_0",
|
||
|
|
ENUM_STATIC_WEIGHT_3 => "WEIGHT_0",
|
||
|
|
ENUM_STATIC_WEIGHT_4 => "WEIGHT_0",
|
||
|
|
ENUM_STATIC_WEIGHT_5 => "WEIGHT_0",
|
||
|
|
ENUM_SYNC_MODE_0 => "ASYNCHRONOUS",
|
||
|
|
ENUM_SYNC_MODE_1 => "ASYNCHRONOUS",
|
||
|
|
ENUM_SYNC_MODE_2 => "ASYNCHRONOUS",
|
||
|
|
ENUM_SYNC_MODE_3 => "ASYNCHRONOUS",
|
||
|
|
ENUM_SYNC_MODE_4 => "ASYNCHRONOUS",
|
||
|
|
ENUM_SYNC_MODE_5 => "ASYNCHRONOUS",
|
||
|
|
ENUM_TEST_MODE => "NORMAL_MODE",
|
||
|
|
ENUM_THLD_JAR1_0 => "THRESHOLD_32",
|
||
|
|
ENUM_THLD_JAR1_1 => "THRESHOLD_32",
|
||
|
|
ENUM_THLD_JAR1_2 => "THRESHOLD_32",
|
||
|
|
ENUM_THLD_JAR1_3 => "THRESHOLD_32",
|
||
|
|
ENUM_THLD_JAR1_4 => "THRESHOLD_32",
|
||
|
|
ENUM_THLD_JAR1_5 => "THRESHOLD_32",
|
||
|
|
ENUM_THLD_JAR2_0 => "THRESHOLD_16",
|
||
|
|
ENUM_THLD_JAR2_1 => "THRESHOLD_16",
|
||
|
|
ENUM_THLD_JAR2_2 => "THRESHOLD_16",
|
||
|
|
ENUM_THLD_JAR2_3 => "THRESHOLD_16",
|
||
|
|
ENUM_THLD_JAR2_4 => "THRESHOLD_16",
|
||
|
|
ENUM_THLD_JAR2_5 => "THRESHOLD_16",
|
||
|
|
ENUM_USE_ALMOST_EMPTY_0 => "EMPTY",
|
||
|
|
ENUM_USE_ALMOST_EMPTY_1 => "EMPTY",
|
||
|
|
ENUM_USE_ALMOST_EMPTY_2 => "EMPTY",
|
||
|
|
ENUM_USE_ALMOST_EMPTY_3 => "EMPTY",
|
||
|
|
ENUM_USER_ECC_EN => "DISABLE",
|
||
|
|
ENUM_USER_PRIORITY_0 => "PRIORITY_1",
|
||
|
|
ENUM_USER_PRIORITY_1 => "PRIORITY_1",
|
||
|
|
ENUM_USER_PRIORITY_2 => "PRIORITY_1",
|
||
|
|
ENUM_USER_PRIORITY_3 => "PRIORITY_1",
|
||
|
|
ENUM_USER_PRIORITY_4 => "PRIORITY_1",
|
||
|
|
ENUM_USER_PRIORITY_5 => "PRIORITY_1",
|
||
|
|
ENUM_WFIFO0_CPORT_MAP => "CMD_PORT_0",
|
||
|
|
ENUM_WFIFO0_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_WFIFO1_CPORT_MAP => "CMD_PORT_0",
|
||
|
|
ENUM_WFIFO1_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_WFIFO2_CPORT_MAP => "CMD_PORT_0",
|
||
|
|
ENUM_WFIFO2_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_WFIFO3_CPORT_MAP => "CMD_PORT_0",
|
||
|
|
ENUM_WFIFO3_RDY_ALMOST_FULL => "NOT_FULL",
|
||
|
|
ENUM_WR_DWIDTH_0 => "DWIDTH_32",
|
||
|
|
ENUM_WR_DWIDTH_1 => "DWIDTH_0",
|
||
|
|
ENUM_WR_DWIDTH_2 => "DWIDTH_0",
|
||
|
|
ENUM_WR_DWIDTH_3 => "DWIDTH_0",
|
||
|
|
ENUM_WR_DWIDTH_4 => "DWIDTH_0",
|
||
|
|
ENUM_WR_DWIDTH_5 => "DWIDTH_0",
|
||
|
|
ENUM_WR_FIFO_IN_USE_0 => "TRUE",
|
||
|
|
ENUM_WR_FIFO_IN_USE_1 => "FALSE",
|
||
|
|
ENUM_WR_FIFO_IN_USE_2 => "FALSE",
|
||
|
|
ENUM_WR_FIFO_IN_USE_3 => "FALSE",
|
||
|
|
ENUM_WR_PORT_INFO_0 => "USE_0",
|
||
|
|
ENUM_WR_PORT_INFO_1 => "USE_NO",
|
||
|
|
ENUM_WR_PORT_INFO_2 => "USE_NO",
|
||
|
|
ENUM_WR_PORT_INFO_3 => "USE_NO",
|
||
|
|
ENUM_WR_PORT_INFO_4 => "USE_NO",
|
||
|
|
ENUM_WR_PORT_INFO_5 => "USE_NO",
|
||
|
|
ENUM_WRITE_ODT_CHIP => "WRITE_CHIP0_ODT0_CHIP1",
|
||
|
|
INTG_MEM_AUTO_PD_CYCLES => 0,
|
||
|
|
INTG_CYC_TO_RLD_JARS_0 => 1,
|
||
|
|
INTG_CYC_TO_RLD_JARS_1 => 1,
|
||
|
|
INTG_CYC_TO_RLD_JARS_2 => 1,
|
||
|
|
INTG_CYC_TO_RLD_JARS_3 => 1,
|
||
|
|
INTG_CYC_TO_RLD_JARS_4 => 1,
|
||
|
|
INTG_CYC_TO_RLD_JARS_5 => 1,
|
||
|
|
INTG_EXTRA_CTL_CLK_ACT_TO_ACT => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_ACT_TO_PCH => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_ARF_PERIOD => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_ARF_TO_VALID => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_PCH_TO_VALID => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_PDN_PERIOD => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_PDN_TO_VALID => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_PCH => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_RD => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_WR => 2,
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC => 2,
|
||
|
|
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP => 2,
|
||
|
|
INTG_EXTRA_CTL_CLK_SRF_TO_VALID => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_PCH => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_RD => 3,
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC => 3,
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP => 3,
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_WR => 0,
|
||
|
|
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP => 0,
|
||
|
|
INTG_MEM_IF_TREFI => 2341,
|
||
|
|
INTG_MEM_IF_TRFC => 34,
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_0 => 0,
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_1 => 0,
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_2 => 0,
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_3 => 0,
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_4 => 0,
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_5 => 0,
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_6 => 0,
|
||
|
|
INTG_RCFG_SUM_WT_PRIORITY_7 => 0,
|
||
|
|
INTG_SUM_WT_PRIORITY_0 => 0,
|
||
|
|
INTG_SUM_WT_PRIORITY_1 => 0,
|
||
|
|
INTG_SUM_WT_PRIORITY_2 => 0,
|
||
|
|
INTG_SUM_WT_PRIORITY_3 => 0,
|
||
|
|
INTG_SUM_WT_PRIORITY_4 => 0,
|
||
|
|
INTG_SUM_WT_PRIORITY_5 => 0,
|
||
|
|
INTG_SUM_WT_PRIORITY_6 => 0,
|
||
|
|
INTG_SUM_WT_PRIORITY_7 => 0,
|
||
|
|
INTG_POWER_SAVING_EXIT_CYCLES => 5,
|
||
|
|
INTG_MEM_CLK_ENTRY_CYCLES => 10,
|
||
|
|
ENUM_ENABLE_BURST_INTERRUPT => "DISABLED",
|
||
|
|
ENUM_ENABLE_BURST_TERMINATE => "DISABLED",
|
||
|
|
AFI_RATE_RATIO => 1,
|
||
|
|
AFI_ADDR_WIDTH => 13,
|
||
|
|
AFI_BANKADDR_WIDTH => 3,
|
||
|
|
AFI_CONTROL_WIDTH => 1,
|
||
|
|
AFI_CS_WIDTH => 1,
|
||
|
|
AFI_DM_WIDTH => 4,
|
||
|
|
AFI_DQ_WIDTH => 32,
|
||
|
|
AFI_ODT_WIDTH => 1,
|
||
|
|
AFI_WRITE_DQS_WIDTH => 2,
|
||
|
|
AFI_RLAT_WIDTH => 6,
|
||
|
|
AFI_WLAT_WIDTH => 6,
|
||
|
|
HARD_PHY => true
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
afi_clk => pll0_afi_clk_clk, -- afi_clk.clk
|
||
|
|
afi_reset_n => p0_afi_reset_reset, -- afi_reset.reset_n
|
||
|
|
ctl_reset_n => p0_ctl_reset_reset, -- ctl_reset.reset_n
|
||
|
|
afi_half_clk => pll0_afi_half_clk_clk, -- afi_half_clk.clk
|
||
|
|
ctl_clk => p0_ctl_clk_clk, -- ctl_clk.clk
|
||
|
|
mp_cmd_clk_0 => mp_cmd_clk_0_clk, -- mp_cmd_clk_0.clk
|
||
|
|
mp_cmd_reset_n_0 => mp_cmd_reset_n_0_reset_n, -- mp_cmd_reset_n_0.reset_n
|
||
|
|
mp_rfifo_clk_0 => mp_rfifo_clk_0_clk, -- mp_rfifo_clk_0.clk
|
||
|
|
mp_rfifo_reset_n_0 => mp_rfifo_reset_n_0_reset_n, -- mp_rfifo_reset_n_0.reset_n
|
||
|
|
mp_wfifo_clk_0 => mp_wfifo_clk_0_clk, -- mp_wfifo_clk_0.clk
|
||
|
|
mp_wfifo_reset_n_0 => mp_wfifo_reset_n_0_reset_n, -- mp_wfifo_reset_n_0.reset_n
|
||
|
|
csr_clk => csr_clk, -- csr_clk.clk
|
||
|
|
csr_reset_n => rst_controller_reset_out_reset_ports_inv, -- csr_reset_n.reset_n
|
||
|
|
avl_ready_0 => avl_ready_0, -- avl_0.waitrequest_n
|
||
|
|
avl_burstbegin_0 => avl_burstbegin_0, -- .beginbursttransfer
|
||
|
|
avl_addr_0 => avl_addr_0, -- .address
|
||
|
|
avl_rdata_valid_0 => avl_rdata_valid_0, -- .readdatavalid
|
||
|
|
avl_rdata_0 => avl_rdata_0, -- .readdata
|
||
|
|
avl_wdata_0 => avl_wdata_0, -- .writedata
|
||
|
|
avl_be_0 => avl_be_0, -- .byteenable
|
||
|
|
avl_read_req_0 => avl_read_req_0, -- .read
|
||
|
|
avl_write_req_0 => avl_write_req_0, -- .write
|
||
|
|
avl_size_0 => avl_size_0, -- .burstcount
|
||
|
|
local_init_done => local_init_done, -- status.local_init_done
|
||
|
|
local_cal_success => local_cal_success, -- .local_cal_success
|
||
|
|
local_cal_fail => local_cal_fail, -- .local_cal_fail
|
||
|
|
csr_write_req => mm_interconnect_2_c0_csr_write, -- csr.write
|
||
|
|
csr_read_req => mm_interconnect_2_c0_csr_read, -- .read
|
||
|
|
csr_waitrequest => mm_interconnect_2_c0_csr_waitrequest, -- .waitrequest
|
||
|
|
csr_addr => mm_interconnect_2_c0_csr_address, -- .address
|
||
|
|
csr_be => mm_interconnect_2_c0_csr_byteenable, -- .byteenable
|
||
|
|
csr_wdata => mm_interconnect_2_c0_csr_writedata, -- .writedata
|
||
|
|
csr_rdata => mm_interconnect_2_c0_csr_readdata, -- .readdata
|
||
|
|
csr_rdata_valid => mm_interconnect_2_c0_csr_readdatavalid, -- .readdatavalid
|
||
|
|
afi_addr => c0_afi_afi_addr, -- afi.afi_addr
|
||
|
|
afi_ba => c0_afi_afi_ba, -- .afi_ba
|
||
|
|
afi_cke => c0_afi_afi_cke, -- .afi_cke
|
||
|
|
afi_cs_n => c0_afi_afi_cs_n, -- .afi_cs_n
|
||
|
|
afi_ras_n => c0_afi_afi_ras_n, -- .afi_ras_n
|
||
|
|
afi_we_n => c0_afi_afi_we_n, -- .afi_we_n
|
||
|
|
afi_cas_n => c0_afi_afi_cas_n, -- .afi_cas_n
|
||
|
|
afi_rst_n => c0_afi_afi_rst_n, -- .afi_rst_n
|
||
|
|
afi_odt => c0_afi_afi_odt, -- .afi_odt
|
||
|
|
afi_mem_clk_disable => c0_afi_afi_mem_clk_disable, -- .afi_mem_clk_disable
|
||
|
|
afi_init_req => c0_afi_afi_init_req, -- .afi_init_req
|
||
|
|
afi_cal_req => c0_afi_afi_cal_req, -- .afi_cal_req
|
||
|
|
afi_dqs_burst => c0_afi_afi_dqs_burst, -- .afi_dqs_burst
|
||
|
|
afi_wdata_valid => c0_afi_afi_wdata_valid, -- .afi_wdata_valid
|
||
|
|
afi_wdata => c0_afi_afi_wdata, -- .afi_wdata
|
||
|
|
afi_dm => c0_afi_afi_dm, -- .afi_dm
|
||
|
|
afi_rdata => p0_afi_afi_rdata, -- .afi_rdata
|
||
|
|
afi_rdata_en => c0_afi_afi_rdata_en, -- .afi_rdata_en
|
||
|
|
afi_rdata_en_full => c0_afi_afi_rdata_en_full, -- .afi_rdata_en_full
|
||
|
|
afi_rdata_valid => p0_afi_afi_rdata_valid, -- .afi_rdata_valid
|
||
|
|
afi_wlat => p0_afi_afi_wlat, -- .afi_wlat
|
||
|
|
afi_rlat => p0_afi_afi_rlat, -- .afi_rlat
|
||
|
|
afi_cal_success => p0_afi_afi_cal_success, -- .afi_cal_success
|
||
|
|
afi_cal_fail => p0_afi_afi_cal_fail, -- .afi_cal_fail
|
||
|
|
cfg_addlat => c0_hard_phy_cfg_cfg_addlat, -- hard_phy_cfg.cfg_addlat
|
||
|
|
cfg_bankaddrwidth => c0_hard_phy_cfg_cfg_bankaddrwidth, -- .cfg_bankaddrwidth
|
||
|
|
cfg_caswrlat => c0_hard_phy_cfg_cfg_caswrlat, -- .cfg_caswrlat
|
||
|
|
cfg_coladdrwidth => c0_hard_phy_cfg_cfg_coladdrwidth, -- .cfg_coladdrwidth
|
||
|
|
cfg_csaddrwidth => c0_hard_phy_cfg_cfg_csaddrwidth, -- .cfg_csaddrwidth
|
||
|
|
cfg_devicewidth => c0_hard_phy_cfg_cfg_devicewidth, -- .cfg_devicewidth
|
||
|
|
cfg_dramconfig => c0_hard_phy_cfg_cfg_dramconfig, -- .cfg_dramconfig
|
||
|
|
cfg_interfacewidth => c0_hard_phy_cfg_cfg_interfacewidth, -- .cfg_interfacewidth
|
||
|
|
cfg_rowaddrwidth => c0_hard_phy_cfg_cfg_rowaddrwidth, -- .cfg_rowaddrwidth
|
||
|
|
cfg_tcl => c0_hard_phy_cfg_cfg_tcl, -- .cfg_tcl
|
||
|
|
cfg_tmrd => c0_hard_phy_cfg_cfg_tmrd, -- .cfg_tmrd
|
||
|
|
cfg_trefi => c0_hard_phy_cfg_cfg_trefi, -- .cfg_trefi
|
||
|
|
cfg_trfc => c0_hard_phy_cfg_cfg_trfc, -- .cfg_trfc
|
||
|
|
cfg_twr => c0_hard_phy_cfg_cfg_twr, -- .cfg_twr
|
||
|
|
io_intaficalfail => p0_io_int_io_intaficalfail, -- io_int.io_intaficalfail
|
||
|
|
io_intaficalsuccess => p0_io_int_io_intaficalsuccess, -- .io_intaficalsuccess
|
||
|
|
mp_cmd_clk_1 => '0', -- (terminated)
|
||
|
|
mp_cmd_reset_n_1 => '1', -- (terminated)
|
||
|
|
mp_cmd_clk_2 => '0', -- (terminated)
|
||
|
|
mp_cmd_reset_n_2 => '1', -- (terminated)
|
||
|
|
mp_cmd_clk_3 => '0', -- (terminated)
|
||
|
|
mp_cmd_reset_n_3 => '1', -- (terminated)
|
||
|
|
mp_cmd_clk_4 => '0', -- (terminated)
|
||
|
|
mp_cmd_reset_n_4 => '1', -- (terminated)
|
||
|
|
mp_cmd_clk_5 => '0', -- (terminated)
|
||
|
|
mp_cmd_reset_n_5 => '1', -- (terminated)
|
||
|
|
mp_rfifo_clk_1 => '0', -- (terminated)
|
||
|
|
mp_rfifo_reset_n_1 => '1', -- (terminated)
|
||
|
|
mp_wfifo_clk_1 => '0', -- (terminated)
|
||
|
|
mp_wfifo_reset_n_1 => '1', -- (terminated)
|
||
|
|
mp_rfifo_clk_2 => '0', -- (terminated)
|
||
|
|
mp_rfifo_reset_n_2 => '1', -- (terminated)
|
||
|
|
mp_wfifo_clk_2 => '0', -- (terminated)
|
||
|
|
mp_wfifo_reset_n_2 => '1', -- (terminated)
|
||
|
|
mp_rfifo_clk_3 => '0', -- (terminated)
|
||
|
|
mp_rfifo_reset_n_3 => '1', -- (terminated)
|
||
|
|
mp_wfifo_clk_3 => '0', -- (terminated)
|
||
|
|
mp_wfifo_reset_n_3 => '1', -- (terminated)
|
||
|
|
avl_ready_1 => open, -- (terminated)
|
||
|
|
avl_burstbegin_1 => '0', -- (terminated)
|
||
|
|
avl_addr_1 => "0", -- (terminated)
|
||
|
|
avl_rdata_valid_1 => open, -- (terminated)
|
||
|
|
avl_rdata_1 => open, -- (terminated)
|
||
|
|
avl_wdata_1 => "0", -- (terminated)
|
||
|
|
avl_be_1 => "0", -- (terminated)
|
||
|
|
avl_read_req_1 => '0', -- (terminated)
|
||
|
|
avl_write_req_1 => '0', -- (terminated)
|
||
|
|
avl_size_1 => "000", -- (terminated)
|
||
|
|
avl_ready_2 => open, -- (terminated)
|
||
|
|
avl_burstbegin_2 => '0', -- (terminated)
|
||
|
|
avl_addr_2 => "0", -- (terminated)
|
||
|
|
avl_rdata_valid_2 => open, -- (terminated)
|
||
|
|
avl_rdata_2 => open, -- (terminated)
|
||
|
|
avl_wdata_2 => "0", -- (terminated)
|
||
|
|
avl_be_2 => "0", -- (terminated)
|
||
|
|
avl_read_req_2 => '0', -- (terminated)
|
||
|
|
avl_write_req_2 => '0', -- (terminated)
|
||
|
|
avl_size_2 => "000", -- (terminated)
|
||
|
|
avl_ready_3 => open, -- (terminated)
|
||
|
|
avl_burstbegin_3 => '0', -- (terminated)
|
||
|
|
avl_addr_3 => "0", -- (terminated)
|
||
|
|
avl_rdata_valid_3 => open, -- (terminated)
|
||
|
|
avl_rdata_3 => open, -- (terminated)
|
||
|
|
avl_wdata_3 => "0", -- (terminated)
|
||
|
|
avl_be_3 => "0", -- (terminated)
|
||
|
|
avl_read_req_3 => '0', -- (terminated)
|
||
|
|
avl_write_req_3 => '0', -- (terminated)
|
||
|
|
avl_size_3 => "000", -- (terminated)
|
||
|
|
avl_ready_4 => open, -- (terminated)
|
||
|
|
avl_burstbegin_4 => '0', -- (terminated)
|
||
|
|
avl_addr_4 => "0", -- (terminated)
|
||
|
|
avl_rdata_valid_4 => open, -- (terminated)
|
||
|
|
avl_rdata_4 => open, -- (terminated)
|
||
|
|
avl_wdata_4 => "0", -- (terminated)
|
||
|
|
avl_be_4 => "0", -- (terminated)
|
||
|
|
avl_read_req_4 => '0', -- (terminated)
|
||
|
|
avl_write_req_4 => '0', -- (terminated)
|
||
|
|
avl_size_4 => "000", -- (terminated)
|
||
|
|
avl_ready_5 => open, -- (terminated)
|
||
|
|
avl_burstbegin_5 => '0', -- (terminated)
|
||
|
|
avl_addr_5 => "0", -- (terminated)
|
||
|
|
avl_rdata_valid_5 => open, -- (terminated)
|
||
|
|
avl_rdata_5 => open, -- (terminated)
|
||
|
|
avl_wdata_5 => "0", -- (terminated)
|
||
|
|
avl_be_5 => "0", -- (terminated)
|
||
|
|
avl_read_req_5 => '0', -- (terminated)
|
||
|
|
avl_write_req_5 => '0', -- (terminated)
|
||
|
|
avl_size_5 => "000", -- (terminated)
|
||
|
|
afi_seq_busy => "0", -- (terminated)
|
||
|
|
afi_ctl_refresh_done => open, -- (terminated)
|
||
|
|
afi_ctl_long_idle => open, -- (terminated)
|
||
|
|
local_multicast => '0', -- (terminated)
|
||
|
|
local_refresh_req => '0', -- (terminated)
|
||
|
|
local_refresh_chip => "0", -- (terminated)
|
||
|
|
local_refresh_ack => open, -- (terminated)
|
||
|
|
local_self_rfsh_req => '0', -- (terminated)
|
||
|
|
local_self_rfsh_chip => "0", -- (terminated)
|
||
|
|
local_self_rfsh_ack => open, -- (terminated)
|
||
|
|
local_deep_powerdn_req => '0', -- (terminated)
|
||
|
|
local_deep_powerdn_chip => "0", -- (terminated)
|
||
|
|
local_deep_powerdn_ack => open, -- (terminated)
|
||
|
|
local_powerdn_ack => open, -- (terminated)
|
||
|
|
local_priority => '0', -- (terminated)
|
||
|
|
bonding_in_1 => "0000", -- (terminated)
|
||
|
|
bonding_in_2 => "000000", -- (terminated)
|
||
|
|
bonding_in_3 => "000000", -- (terminated)
|
||
|
|
bonding_out_1 => open, -- (terminated)
|
||
|
|
bonding_out_2 => open, -- (terminated)
|
||
|
|
bonding_out_3 => open -- (terminated)
|
||
|
|
);
|
||
|
|
|
||
|
|
oct0 : component altera_mem_if_oct_cyclonev
|
||
|
|
generic map (
|
||
|
|
OCT_TERM_CONTROL_WIDTH => 16
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
oct_rzqin => oct_rzqin, -- oct.rzqin
|
||
|
|
seriesterminationcontrol => oct0_oct_sharing_seriesterminationcontrol, -- oct_sharing.seriesterminationcontrol
|
||
|
|
parallelterminationcontrol => oct0_oct_sharing_parallelterminationcontrol -- .parallelterminationcontrol
|
||
|
|
);
|
||
|
|
|
||
|
|
dll0 : component altera_mem_if_dll_cyclonev
|
||
|
|
generic map (
|
||
|
|
DLL_DELAY_CTRL_WIDTH => 7,
|
||
|
|
DLL_OFFSET_CTRL_WIDTH => 6,
|
||
|
|
DELAY_BUFFER_MODE => "HIGH",
|
||
|
|
DELAY_CHAIN_LENGTH => 8,
|
||
|
|
DLL_INPUT_FREQUENCY_PS_STR => "3333 ps"
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
clk => p0_dll_clk_clk, -- clk.clk
|
||
|
|
dll_pll_locked => p0_dll_sharing_dll_pll_locked, -- dll_sharing.dll_pll_locked
|
||
|
|
dll_delayctrl => dll0_dll_sharing_dll_delayctrl -- .dll_delayctrl
|
||
|
|
);
|
||
|
|
|
||
|
|
if_csr_m0 : component ddr3_dmaster
|
||
|
|
port map (
|
||
|
|
clk_clk => csr_clk, -- clk.clk
|
||
|
|
clk_reset_reset => csr_reset_n_ports_inv, -- clk_reset.reset
|
||
|
|
master_address => if_csr_m0_master_address, -- master.address
|
||
|
|
master_readdata => if_csr_m0_master_readdata, -- .readdata
|
||
|
|
master_read => if_csr_m0_master_read, -- .read
|
||
|
|
master_write => if_csr_m0_master_write, -- .write
|
||
|
|
master_writedata => if_csr_m0_master_writedata, -- .writedata
|
||
|
|
master_waitrequest => if_csr_m0_master_waitrequest, -- .waitrequest
|
||
|
|
master_readdatavalid => if_csr_m0_master_readdatavalid, -- .readdatavalid
|
||
|
|
master_byteenable => if_csr_m0_master_byteenable, -- .byteenable
|
||
|
|
master_reset_reset => open -- master_reset.reset
|
||
|
|
);
|
||
|
|
|
||
|
|
mm_interconnect_1 : component ddr3_mm_interconnect_1
|
||
|
|
port map (
|
||
|
|
p0_avl_clk_clk => p0_avl_clk_clk, -- p0_avl_clk.clk
|
||
|
|
dmaster_clk_reset_reset_bridge_in_reset_reset => p0_avl_reset_reset_ports_inv, -- dmaster_clk_reset_reset_bridge_in_reset.reset
|
||
|
|
dmaster_master_translator_reset_reset_bridge_in_reset_reset => p0_avl_reset_reset_ports_inv, -- dmaster_master_translator_reset_reset_bridge_in_reset.reset
|
||
|
|
dmaster_master_address => dmaster_master_address, -- dmaster_master.address
|
||
|
|
dmaster_master_waitrequest => dmaster_master_waitrequest, -- .waitrequest
|
||
|
|
dmaster_master_byteenable => dmaster_master_byteenable, -- .byteenable
|
||
|
|
dmaster_master_read => dmaster_master_read, -- .read
|
||
|
|
dmaster_master_readdata => dmaster_master_readdata, -- .readdata
|
||
|
|
dmaster_master_readdatavalid => dmaster_master_readdatavalid, -- .readdatavalid
|
||
|
|
dmaster_master_write => dmaster_master_write, -- .write
|
||
|
|
dmaster_master_writedata => dmaster_master_writedata, -- .writedata
|
||
|
|
s0_seq_debug_address => mm_interconnect_1_s0_seq_debug_address, -- s0_seq_debug.address
|
||
|
|
s0_seq_debug_write => mm_interconnect_1_s0_seq_debug_write, -- .write
|
||
|
|
s0_seq_debug_read => mm_interconnect_1_s0_seq_debug_read, -- .read
|
||
|
|
s0_seq_debug_readdata => mm_interconnect_1_s0_seq_debug_readdata, -- .readdata
|
||
|
|
s0_seq_debug_writedata => mm_interconnect_1_s0_seq_debug_writedata, -- .writedata
|
||
|
|
s0_seq_debug_burstcount => mm_interconnect_1_s0_seq_debug_burstcount, -- .burstcount
|
||
|
|
s0_seq_debug_byteenable => mm_interconnect_1_s0_seq_debug_byteenable, -- .byteenable
|
||
|
|
s0_seq_debug_readdatavalid => mm_interconnect_1_s0_seq_debug_readdatavalid, -- .readdatavalid
|
||
|
|
s0_seq_debug_waitrequest => mm_interconnect_1_s0_seq_debug_waitrequest -- .waitrequest
|
||
|
|
);
|
||
|
|
|
||
|
|
mm_interconnect_2 : component ddr3_mm_interconnect_2
|
||
|
|
port map (
|
||
|
|
csr_clk_out_clk_clk => csr_clk, -- csr_clk_out_clk.clk
|
||
|
|
if_csr_m0_clk_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- if_csr_m0_clk_reset_reset_bridge_in_reset.reset
|
||
|
|
p0_csr_reset_n_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- p0_csr_reset_n_reset_bridge_in_reset.reset
|
||
|
|
if_csr_m0_master_address => if_csr_m0_master_address, -- if_csr_m0_master.address
|
||
|
|
if_csr_m0_master_waitrequest => if_csr_m0_master_waitrequest, -- .waitrequest
|
||
|
|
if_csr_m0_master_byteenable => if_csr_m0_master_byteenable, -- .byteenable
|
||
|
|
if_csr_m0_master_read => if_csr_m0_master_read, -- .read
|
||
|
|
if_csr_m0_master_readdata => if_csr_m0_master_readdata, -- .readdata
|
||
|
|
if_csr_m0_master_readdatavalid => if_csr_m0_master_readdatavalid, -- .readdatavalid
|
||
|
|
if_csr_m0_master_write => if_csr_m0_master_write, -- .write
|
||
|
|
if_csr_m0_master_writedata => if_csr_m0_master_writedata, -- .writedata
|
||
|
|
c0_csr_address => mm_interconnect_2_c0_csr_address, -- c0_csr.address
|
||
|
|
c0_csr_write => mm_interconnect_2_c0_csr_write, -- .write
|
||
|
|
c0_csr_read => mm_interconnect_2_c0_csr_read, -- .read
|
||
|
|
c0_csr_readdata => mm_interconnect_2_c0_csr_readdata, -- .readdata
|
||
|
|
c0_csr_writedata => mm_interconnect_2_c0_csr_writedata, -- .writedata
|
||
|
|
c0_csr_byteenable => mm_interconnect_2_c0_csr_byteenable, -- .byteenable
|
||
|
|
c0_csr_readdatavalid => mm_interconnect_2_c0_csr_readdatavalid, -- .readdatavalid
|
||
|
|
c0_csr_waitrequest => mm_interconnect_2_c0_csr_waitrequest, -- .waitrequest
|
||
|
|
p0_csr_address => mm_interconnect_2_p0_csr_address, -- p0_csr.address
|
||
|
|
p0_csr_write => mm_interconnect_2_p0_csr_write, -- .write
|
||
|
|
p0_csr_read => mm_interconnect_2_p0_csr_read, -- .read
|
||
|
|
p0_csr_readdata => mm_interconnect_2_p0_csr_readdata, -- .readdata
|
||
|
|
p0_csr_writedata => mm_interconnect_2_p0_csr_writedata, -- .writedata
|
||
|
|
p0_csr_byteenable => mm_interconnect_2_p0_csr_byteenable, -- .byteenable
|
||
|
|
p0_csr_readdatavalid => mm_interconnect_2_p0_csr_readdatavalid, -- .readdatavalid
|
||
|
|
p0_csr_waitrequest => mm_interconnect_2_p0_csr_waitrequest -- .waitrequest
|
||
|
|
);
|
||
|
|
|
||
|
|
rst_controller : component altera_reset_controller
|
||
|
|
generic map (
|
||
|
|
NUM_RESET_INPUTS => 1,
|
||
|
|
OUTPUT_RESET_SYNC_EDGES => "deassert",
|
||
|
|
SYNC_DEPTH => 2,
|
||
|
|
RESET_REQUEST_PRESENT => 0,
|
||
|
|
RESET_REQ_WAIT_TIME => 1,
|
||
|
|
MIN_RST_ASSERTION_TIME => 3,
|
||
|
|
RESET_REQ_EARLY_DSRT_TIME => 1,
|
||
|
|
USE_RESET_REQUEST_IN0 => 0,
|
||
|
|
USE_RESET_REQUEST_IN1 => 0,
|
||
|
|
USE_RESET_REQUEST_IN2 => 0,
|
||
|
|
USE_RESET_REQUEST_IN3 => 0,
|
||
|
|
USE_RESET_REQUEST_IN4 => 0,
|
||
|
|
USE_RESET_REQUEST_IN5 => 0,
|
||
|
|
USE_RESET_REQUEST_IN6 => 0,
|
||
|
|
USE_RESET_REQUEST_IN7 => 0,
|
||
|
|
USE_RESET_REQUEST_IN8 => 0,
|
||
|
|
USE_RESET_REQUEST_IN9 => 0,
|
||
|
|
USE_RESET_REQUEST_IN10 => 0,
|
||
|
|
USE_RESET_REQUEST_IN11 => 0,
|
||
|
|
USE_RESET_REQUEST_IN12 => 0,
|
||
|
|
USE_RESET_REQUEST_IN13 => 0,
|
||
|
|
USE_RESET_REQUEST_IN14 => 0,
|
||
|
|
USE_RESET_REQUEST_IN15 => 0,
|
||
|
|
ADAPT_RESET_REQUEST => 0
|
||
|
|
)
|
||
|
|
port map (
|
||
|
|
reset_in0 => csr_reset_n_ports_inv, -- reset_in0.reset
|
||
|
|
clk => csr_clk, -- clk.clk
|
||
|
|
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
|
||
|
|
reset_req => open, -- (terminated)
|
||
|
|
reset_req_in0 => '0', -- (terminated)
|
||
|
|
reset_in1 => '0', -- (terminated)
|
||
|
|
reset_req_in1 => '0', -- (terminated)
|
||
|
|
reset_in2 => '0', -- (terminated)
|
||
|
|
reset_req_in2 => '0', -- (terminated)
|
||
|
|
reset_in3 => '0', -- (terminated)
|
||
|
|
reset_req_in3 => '0', -- (terminated)
|
||
|
|
reset_in4 => '0', -- (terminated)
|
||
|
|
reset_req_in4 => '0', -- (terminated)
|
||
|
|
reset_in5 => '0', -- (terminated)
|
||
|
|
reset_req_in5 => '0', -- (terminated)
|
||
|
|
reset_in6 => '0', -- (terminated)
|
||
|
|
reset_req_in6 => '0', -- (terminated)
|
||
|
|
reset_in7 => '0', -- (terminated)
|
||
|
|
reset_req_in7 => '0', -- (terminated)
|
||
|
|
reset_in8 => '0', -- (terminated)
|
||
|
|
reset_req_in8 => '0', -- (terminated)
|
||
|
|
reset_in9 => '0', -- (terminated)
|
||
|
|
reset_req_in9 => '0', -- (terminated)
|
||
|
|
reset_in10 => '0', -- (terminated)
|
||
|
|
reset_req_in10 => '0', -- (terminated)
|
||
|
|
reset_in11 => '0', -- (terminated)
|
||
|
|
reset_req_in11 => '0', -- (terminated)
|
||
|
|
reset_in12 => '0', -- (terminated)
|
||
|
|
reset_req_in12 => '0', -- (terminated)
|
||
|
|
reset_in13 => '0', -- (terminated)
|
||
|
|
reset_req_in13 => '0', -- (terminated)
|
||
|
|
reset_in14 => '0', -- (terminated)
|
||
|
|
reset_req_in14 => '0', -- (terminated)
|
||
|
|
reset_in15 => '0', -- (terminated)
|
||
|
|
reset_req_in15 => '0' -- (terminated)
|
||
|
|
);
|
||
|
|
|
||
|
|
p0_avl_reset_reset_ports_inv <= not p0_avl_reset_reset;
|
||
|
|
|
||
|
|
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
|
||
|
|
|
||
|
|
afi_clk <= pll0_afi_clk_clk;
|
||
|
|
|
||
|
|
afi_half_clk <= pll0_afi_half_clk_clk;
|
||
|
|
|
||
|
|
afi_reset_n <= p0_afi_reset_reset;
|
||
|
|
|
||
|
|
pll_write_clk <= pll0_pll_sharing_pll_write_clk;
|
||
|
|
|
||
|
|
pll_avl_clk <= pll0_pll_sharing_pll_avl_clk;
|
||
|
|
|
||
|
|
pll_write_clk_pre_phy_clk <= pll0_pll_sharing_pll_write_clk_pre_phy_clk;
|
||
|
|
|
||
|
|
pll_addr_cmd_clk <= pll0_pll_sharing_pll_addr_cmd_clk;
|
||
|
|
|
||
|
|
pll_config_clk <= pll0_pll_sharing_pll_config_clk;
|
||
|
|
|
||
|
|
pll_avl_phy_clk <= pll0_pll_sharing_pll_avl_phy_clk;
|
||
|
|
|
||
|
|
afi_phy_clk <= pll0_pll_sharing_afi_phy_clk;
|
||
|
|
|
||
|
|
pll_mem_clk <= pll0_pll_sharing_pll_mem_clk;
|
||
|
|
|
||
|
|
pll_locked <= pll0_pll_sharing_pll_locked;
|
||
|
|
|
||
|
|
pll_mem_phy_clk <= pll0_pll_sharing_pll_mem_phy_clk;
|
||
|
|
|
||
|
|
end architecture rtl; -- of ddr3_0002
|