42 lines
1.6 KiB
VHDL
42 lines
1.6 KiB
VHDL
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-- An MxS Wishbone crossbar switch.
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--
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-- All masters, slaves, and the crossbar itself must share the same WB clock.
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-- All participants must support the same data bus width.
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--
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-- If a master raises STB_O with an address not mapped by the crossbar,
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-- ERR_I will be raised. If the crossbar has overlapping address ranges,
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-- the lowest numbered slave is selected. If two masters address the same
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-- slave simultaneously, the lowest numbered master is granted access.
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--
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-- The implementation of this crossbar locks a master to a slave so long as
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-- CYC_O is held high. If the master tries to address outside the slave's
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-- address range, ERR_I will be raised.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.wishbone_package.all;
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package crossbar_package is
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component crossbar is
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generic(
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masters : integer := 2;
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slaves : integer := 1;
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async : boolean := false
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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-- Master connections (INTERCON is a slave)
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slave_i : in wishbone_slave_in_vector(masters-1 downto 0);
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slave_o : out wishbone_slave_out_vector(masters-1 downto 0);
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-- Slave connections (INTERCON is a master)
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master_i : in wishbone_master_in_vector(slaves-1 downto 0);
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master_o : out wishbone_master_out_vector(slaves-1 downto 0);
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-- Address of the slaves connected
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address : in wishbone_address_vector(slaves-1 downto 0);
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mask : in wishbone_address_vector(slaves-1 downto 0)
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);
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end component;
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end;
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