241 lines
9.0 KiB
VHDL
241 lines
9.0 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.wishbone_package.all;
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-- Assumption: wishbone_data_width >= wishbone_address_Width
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entity dma is
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generic(
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-- Value 0 cannot stream
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-- Value 1 only slaves with async ACK can stream
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-- Value 2 only slaves with combined latency = 2 can stream
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-- Value 3 only slaves with combined latency = 6 can stream
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-- Value 4 only slaves with combined latency = 14 can stream
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-- ....
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logRingLen : integer := 4
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);
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port(
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-- Common wishbone signals
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clk : in std_logic;
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rst : in std_logic;
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-- Slave control port
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slave_i : in wishbone_slave_in;
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slave_o : out wishbone_slave_out;
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-- Master reader port
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r_master_i : in wishbone_master_in;
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r_master_o : out wishbone_master_out;
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-- Master writer port
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w_master_i : in wishbone_master_in;
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w_master_o : out wishbone_master_out;
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-- Pulsed high completion signal
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interrupt : out std_logic
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);
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end dma;
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architecture rtl of dma is
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constant ringLen : integer := 2**logRingLen;
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type ring_t is array (ringLen-1 downto 0) of wishbone_data;
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-- Ring buffer for shipping data from read master to write master
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signal ring : ring_t;
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-- State registers (pointer into the ring)
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-- Invariant: read_issue_offset >= read_result_offset >= write_issue_offset >= write_result_offset
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-- read_issue_offset - write_result_offset <= ringLen (*NOT* strict '<')
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signal read_issue_offset : unsigned(logRingLen downto 0);
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signal read_result_offset : unsigned(logRingLen downto 0);
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signal write_issue_offset : unsigned(logRingLen downto 0);
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signal write_result_offset : unsigned(logRingLen downto 0);
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-- DMA control registers
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signal read_issue_address : wishbone_address;
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signal write_issue_address : wishbone_address;
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signal read_stride : wishbone_address;
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signal write_stride : wishbone_address;
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signal transfer_count : wishbone_address;
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-- result status: fail/ok ?
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-- Registered wishbone control signals
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signal r_master_o_CYC : std_logic;
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signal w_master_o_CYC : std_logic;
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signal r_master_o_STB : std_logic;
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signal w_master_o_STB : std_logic;
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signal slave_o_ACK : std_logic;
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signal slave_o_DAT : wishbone_data;
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function active_high(x : boolean)
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return std_logic is
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begin
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if (x) then
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return '1';
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else
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return '0';
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end if;
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end active_high;
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function index(x : unsigned(logRingLen downto 0))
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return integer is
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begin
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if logRingLen > 0 then
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return to_integer(x(logRingLen-1 downto 0));
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else
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return 0;
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end if;
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end index;
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procedure update(signal o : out wishbone_address) is
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begin
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for i in (wishbone_data_width/8)-1 downto 0 loop
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if slave_i.SEL(i) = '1' then
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o(i*8+7 downto i*8) <= slave_i.DAT(i*8+7 downto i*8);
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end if;
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end loop;
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end update;
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begin
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-- Hard-wired slave pins
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slave_o.ACK <= slave_o_ACK;
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slave_o.ERR <= '0';
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slave_o.RTY <= '0';
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slave_o.STALL <= '0';
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slave_o.DAT <= slave_o_DAT;
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-- Hard-wired master pins
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r_master_o.CYC <= r_master_o_CYC;
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w_master_o.CYC <= w_master_o_CYC;
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r_master_o.STB <= r_master_o_STB;
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w_master_o.STB <= w_master_o_STB;
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r_master_o.ADR <= read_issue_address;
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w_master_o.ADR <= write_issue_address;
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r_master_o.SEL <= (others => '1');
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w_master_o.SEL <= (others => '1');
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r_master_o.WE <= '0';
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w_master_o.WE <= '1';
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r_master_o.DAT <= (others => '0');
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w_master_o.DAT <= ring(index(write_issue_offset));
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main : process(clk)
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variable read_issue_progress : boolean;
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variable read_result_progress : boolean;
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variable write_issue_progress : boolean;
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variable write_result_progress : boolean;
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variable new_read_issue_offset : unsigned(logRingLen downto 0);
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variable new_read_result_offset : unsigned(logRingLen downto 0);
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variable new_write_issue_offset : unsigned(logRingLen downto 0);
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variable new_write_result_offset : unsigned(logRingLen downto 0);
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variable new_transfer_count : wishbone_address;
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variable ring_boundary : boolean;
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variable ring_high : boolean;
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variable ring_full : boolean;
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variable ring_empty : boolean;
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variable done_transfer : boolean;
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begin
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if (rising_edge(clk)) then
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if (rst = '1') then
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read_issue_offset <= (others => '0');
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read_result_offset <= (others => '0');
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write_issue_offset <= (others => '0');
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write_result_offset <= (others => '0');
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read_issue_address <= (others => '0');
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write_issue_address <= (others => '0');
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read_stride <= (others => '0');
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write_stride <= (others => '0');
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transfer_count <= (others => '0');
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r_master_o_CYC <= '0';
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w_master_o_CYC <= '0';
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r_master_o_STB <= '0';
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w_master_o_STB <= '0';
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slave_o_ACK <= '0';
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slave_o_DAT <= (others => '0');
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interrupt <= '0';
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else
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-- Output any read the user requests
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case to_integer(unsigned(slave_i.ADR(4 downto 2))) is
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when 0 => slave_o_DAT <= read_issue_address;
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when 1 => slave_o_DAT <= write_issue_address;
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when 2 => slave_o_DAT <= read_stride;
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when 3 => slave_o_DAT <= write_stride;
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when 4 => slave_o_DAT <= transfer_count;
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when others => slave_o_DAT <= (others => '0');
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end case;
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-- Detect bus progress
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read_issue_progress := r_master_o_STB = '1' and r_master_i.STALL = '0';
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write_issue_progress := w_master_o_STB = '1' and w_master_i.STALL = '0';
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read_result_progress := r_master_o_CYC = '1' and (r_master_i.ACK = '1' or r_master_i.ERR = '1' or r_master_i.RTY = '1');
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write_result_progress := w_master_o_CYC = '1' and (w_master_i.ACK = '1' or w_master_i.ERR = '1' or w_master_i.RTY = '1');
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-- Advance read pointers
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if read_issue_progress then
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read_issue_address <= std_logic_vector(unsigned(read_issue_address) + unsigned(read_stride));
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new_read_issue_offset := read_issue_offset + 1;
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new_transfer_count := std_logic_vector(unsigned(transfer_count) - 1);
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else
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new_read_issue_offset := read_issue_offset;
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new_transfer_count := transfer_count;
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end if;
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if read_result_progress then
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ring(index(read_result_offset)) <= r_master_i.DAT;
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new_read_result_offset := read_result_offset + 1;
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else
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new_read_result_offset := read_result_offset;
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end if;
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-- Advance write pointers
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if write_issue_progress then
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write_issue_address <= std_logic_vector(unsigned(write_issue_address) + unsigned(write_stride));
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new_write_issue_offset := write_issue_offset + 1;
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else
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new_write_issue_offset := write_issue_offset;
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end if;
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if write_result_progress then
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new_write_result_offset := write_result_offset + 1;
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else
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new_write_result_offset := write_result_offset;
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end if;
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ring_boundary := index(new_read_issue_offset) = index(new_write_result_offset);
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ring_high := new_read_issue_offset(logRingLen) /= new_write_result_offset(logRingLen);
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ring_full := ring_boundary and ring_high;
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ring_empty := ring_boundary and not ring_high;
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-- Shorten the critical path by comparing to the undecremented value
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--done_transfer := unsigned(new_transfer_count) = 0;
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done_transfer := unsigned(transfer_count(wishbone_address_width-1 downto 1)) = 0
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and (read_issue_progress or transfer_count(0) = '0');
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r_master_o_STB <= active_high (not ring_full and not done_transfer);
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r_master_o_CYC <= active_high((not ring_full and not done_transfer) or
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(new_read_result_offset /= new_read_issue_offset));
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w_master_o_STB <= active_high (new_write_issue_offset /= new_read_result_offset);
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w_master_o_CYC <= active_high (new_write_result_offset /= new_read_result_offset);
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interrupt <= active_high (write_result_progress and done_transfer and ring_empty);
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transfer_count <= new_transfer_count;
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read_issue_offset <= new_read_issue_offset;
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read_result_offset <= new_read_result_offset;
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write_issue_offset <= new_write_issue_offset;
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write_result_offset <= new_write_result_offset;
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-- Control logic
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if (slave_i.CYC = '1' and slave_i.STB = '1' and slave_i.WE = '1') then
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case to_integer(unsigned(slave_i.ADR(4 downto 2))) is
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when 0 => update(read_issue_address);
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when 1 => update(write_issue_address);
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when 2 => update(read_stride);
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when 3 => update(write_stride);
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when 4 => update(transfer_count);
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when others => null;
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end case;
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end if;
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slave_o_ACK <= slave_i.CYC and slave_i.STB;
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end if;
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end if;
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end process;
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end rtl;
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