76 lines
2.7 KiB
VHDL
76 lines
2.7 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package wishbone_package is
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constant wishbone_address_width : integer := 32;
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constant wishbone_data_width : integer := 32;
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subtype wishbone_address is
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std_logic_vector(wishbone_address_width-1 downto 0);
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subtype wishbone_data is
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std_logic_vector(wishbone_data_width-1 downto 0);
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subtype wishbone_byte_select is
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std_logic_vector((wishbone_address_width/8)-1 downto 0);
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subtype wishbone_cycle_type is
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std_logic_vector(2 downto 0);
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subtype wishbone_burst_type is
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std_logic_vector(1 downto 0);
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-- A B.4 Wishbone pipelined master
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-- Pipelined wishbone is always LOCKed during CYC (else ACKs would get lost)
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type wishbone_master_out is record
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CYC : std_logic;
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STB : std_logic;
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ADR : wishbone_address;
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SEL : wishbone_byte_select;
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WE : std_logic;
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DAT : wishbone_data;
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end record wishbone_master_out;
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subtype wishbone_slave_in is wishbone_master_out;
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type wishbone_slave_out is record
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ACK : std_logic;
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ERR : std_logic;
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RTY : std_logic;
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STALL : std_logic;
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DAT : wishbone_data;
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end record wishbone_slave_out;
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subtype wishbone_master_in is wishbone_slave_out;
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type wishbone_v3_master_out is record
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CYC : std_logic;
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STB : std_logic;
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ADR : wishbone_address;
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SEL : wishbone_byte_select;
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WE : std_logic;
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LOCK : std_logic;
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DAT : wishbone_data;
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CTI : wishbone_cycle_type;
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BTE : wishbone_burst_type;
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end record wishbone_v3_master_out;
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subtype wishbone_v3_slave_in is wishbone_v3_master_out;
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type wishbone_v3_slave_out is record
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ACK : std_logic;
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ERR : std_logic;
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RTY : std_logic;
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DAT : wishbone_data;
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end record wishbone_v3_slave_out;
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subtype wishbone_v3_master_in is wishbone_v3_slave_out;
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type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out;
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type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out;
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subtype wishbone_slave_in_vector is wishbone_master_out_vector;
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subtype wishbone_master_in_vector is wishbone_slave_out_vector;
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type wishbone_v3_master_out_vector is array (natural range <>) of wishbone_v3_master_out;
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type wishbone_v3_slave_out_vector is array (natural range <>) of wishbone_v3_slave_out;
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subtype wishbone_v3_slave_in_vector is wishbone_v3_master_out_vector;
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subtype wishbone_v3_master_in_vector is wishbone_v3_slave_out_vector;
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type wishbone_address_vector is array (natural range <>) of wishbone_address;
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type wishbone_data_vector is array (natural range <>) of wishbone_data;
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end wishbone_package;
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