60 lines
5.4 KiB
Plaintext
60 lines
5.4 KiB
Plaintext
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component ddr3 is
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port (
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pll_ref_clk : in std_logic := 'X'; -- clk
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global_reset_n : in std_logic := 'X'; -- reset_n
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soft_reset_n : in std_logic := 'X'; -- reset_n
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afi_clk : out std_logic; -- clk
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afi_half_clk : out std_logic; -- clk
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afi_reset_n : out std_logic; -- reset_n
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afi_reset_export_n : out std_logic; -- reset_n
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mem_a : out std_logic_vector(12 downto 0); -- mem_a
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mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
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mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
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mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
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mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
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mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
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mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
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mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
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mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
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mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
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mem_reset_n : out std_logic; -- mem_reset_n
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mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
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mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
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mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
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mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
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avl_ready_0 : out std_logic; -- waitrequest_n
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avl_burstbegin_0 : in std_logic := 'X'; -- beginbursttransfer
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avl_addr_0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
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avl_rdata_valid_0 : out std_logic; -- readdatavalid
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avl_rdata_0 : out std_logic_vector(31 downto 0); -- readdata
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avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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avl_be_0 : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
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avl_read_req_0 : in std_logic := 'X'; -- read
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avl_write_req_0 : in std_logic := 'X'; -- write
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avl_size_0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
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mp_cmd_clk_0_clk : in std_logic := 'X'; -- clk
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mp_cmd_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n
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mp_rfifo_clk_0_clk : in std_logic := 'X'; -- clk
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mp_rfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n
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mp_wfifo_clk_0_clk : in std_logic := 'X'; -- clk
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mp_wfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n
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csr_clk : in std_logic := 'X'; -- clk
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csr_reset_n : in std_logic := 'X'; -- reset_n
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local_init_done : out std_logic; -- local_init_done
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local_cal_success : out std_logic; -- local_cal_success
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local_cal_fail : out std_logic; -- local_cal_fail
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oct_rzqin : in std_logic := 'X'; -- rzqin
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pll_mem_clk : out std_logic; -- pll_mem_clk
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pll_write_clk : out std_logic; -- pll_write_clk
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pll_locked : out std_logic; -- pll_locked
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pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
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pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
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pll_avl_clk : out std_logic; -- pll_avl_clk
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pll_config_clk : out std_logic; -- pll_config_clk
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pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
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afi_phy_clk : out std_logic; -- afi_phy_clk
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pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
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);
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end component ddr3;
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