14 lines
461 B
Plaintext
14 lines
461 B
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<simPackage>
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<file path="ddr3_sim/ddr3/ddr3_pll0.vho" type="VHDL" library="pll0" />
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<file
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path="ddr3_sim/ddr3/ddr3_pll0_sim_delay.vhd"
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type="VHDL"
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library="pll0" />
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<file path="ddr3_sim/ddr3/ddr3_0002.vhd" type="VHDL" library="ddr3" />
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<file path="ddr3_sim/ddr3.vhd" type="VHDL" />
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<topLevel name="ddr3" />
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<deviceFamily name="cyclonev" />
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<modelMap controllerPath="ddr3" modelPath="ddr3" />
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</simPackage>
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