71 lines
2.6 KiB
Coq
71 lines
2.6 KiB
Coq
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// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// --------------------------------------------------------------------------------
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//| Avalon ST Idle Remover
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// --------------------------------------------------------------------------------
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`timescale 1ns / 100ps
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module altera_avalon_st_idle_remover (
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// Interface: clk
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input clk,
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input reset_n,
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// Interface: ST in
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output reg in_ready,
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input in_valid,
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input [7: 0] in_data,
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// Interface: ST out
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input out_ready,
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output reg out_valid,
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output reg [7: 0] out_data
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);
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// ---------------------------------------------------------------------
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//| Signal Declarations
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// ---------------------------------------------------------------------
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reg received_esc;
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wire escape_char, idle_char;
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// ---------------------------------------------------------------------
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//| Thingofamagick
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// ---------------------------------------------------------------------
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assign idle_char = (in_data == 8'h4a);
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assign escape_char = (in_data == 8'h4d);
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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received_esc <= 0;
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end else begin
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if (in_valid & in_ready) begin
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if (escape_char & ~received_esc) begin
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received_esc <= 1;
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end else if (out_valid) begin
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received_esc <= 0;
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end
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end
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end
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end
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always @* begin
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in_ready = out_ready;
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//out valid when in_valid. Except when we get idle or escape
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//however, if we have received an escape character, then we are valid
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out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
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out_data = received_esc ? (in_data ^ 8'h20) : in_data;
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end
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endmodule
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