264 lines
11 KiB
Systemverilog
264 lines
11 KiB
Systemverilog
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// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/main/ip/merlin/altera_merlin_axi_master_ni/address_alignment.sv#3 $
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// $Revision: #3 $
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// $Date: 2012/07/11 $
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// $Author: tgngo $
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//-----------------------------------------
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// Address alignment:
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// This component will aglin input address with input size
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// Support address increment with butst type and burstwrap value
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//-----------------------------------------
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`timescale 1 ns / 1 ns
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module altera_merlin_address_alignment
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#(
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parameter
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ADDR_W = 12,
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BURSTWRAP_W = 12,
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TYPE_W = 2,
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SIZE_W = 3,
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INCREMENT_ADDRESS = 1,
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NUMSYMBOLS = 8,
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SELECT_BITS = log2(NUMSYMBOLS),
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IN_DATA_W = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W,
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OUT_DATA_W = ADDR_W + SELECT_BITS
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)
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(
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input clk,
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input reset,
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input [IN_DATA_W-1:0] in_data, // in_data = {wrap_boundary, address, type, size}
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input in_valid,
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//output in_ready,
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input in_sop,
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input in_eop,
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output reg [OUT_DATA_W-1:0] out_data,
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input out_ready
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//output out_valid
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);
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typedef enum bit [1:0]
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{
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FIXED = 2'b00,
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INCR = 2'b01,
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WRAP = 2'b10,
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RESERVED = 2'b11
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} AxiBurstType;
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//----------------------------------------------------
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// AXSIZE decoding
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//
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// Turns the axsize value into the actual number of bytes
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// being transferred.
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// ---------------------------------------------------
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function reg[9:0] bytes_in_transfer;
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input [SIZE_W-1:0] axsize;
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case (axsize)
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4'b0000: bytes_in_transfer = 10'b0000000001;
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4'b0001: bytes_in_transfer = 10'b0000000010;
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4'b0010: bytes_in_transfer = 10'b0000000100;
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4'b0011: bytes_in_transfer = 10'b0000001000;
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4'b0100: bytes_in_transfer = 10'b0000010000;
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4'b0101: bytes_in_transfer = 10'b0000100000;
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4'b0110: bytes_in_transfer = 10'b0001000000;
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4'b0111: bytes_in_transfer = 10'b0010000000;
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4'b1000: bytes_in_transfer = 10'b0100000000;
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4'b1001: bytes_in_transfer = 10'b1000000000;
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default: bytes_in_transfer = 10'b0000000001;
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endcase
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endfunction
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//--------------------------------------
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// Burst type decode
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//--------------------------------------
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AxiBurstType write_burst_type;
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function AxiBurstType burst_type_decode
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(
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input [1:0] axburst
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);
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AxiBurstType burst_type;
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begin
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case (axburst)
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2'b00 : burst_type = FIXED;
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2'b01 : burst_type = INCR;
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2'b10 : burst_type = WRAP;
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2'b11 : burst_type = RESERVED;
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default : burst_type = INCR;
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endcase
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return burst_type;
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end
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endfunction
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//----------------------------------------------------
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// Ubiquitous, familiar log2 function
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//----------------------------------------------------
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function integer log2;
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input integer value;
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value = value - 1;
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for(log2 = 0; value > 0; log2 = log2 + 1)
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value = value >> 1;
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endfunction
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//------------------------------------------------------------------------
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// This component will read address and size and check
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// if this is aligned or not. If not then it will align this address to the size
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// of the transfer:
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// Check alignment:
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// - With data width, can define maximun how many lower bits of address to indicate this
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// address align to the size
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// - Ex: 32 bits data => size can be: 1, 2, 4 bytes
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// For 4 bytes: when 2 lower bits of address equal 0, this is aligned address
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// addr=00|00| (0), 01|00| (4) => align to size of 4 bytes
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// addr=00|01| (1) => start addr at 1, is not aligned to size 4 byte
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// For 2 bytes: use last one bit to indicate algined or not
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// addr=000|0| (0), 001|0| (2) => align to size of 2 bytes
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// addr=000|1| (1), 001|1| (3) => not align to 2 bytes
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// As size runtime change, creat mask and change accordingly to size, can detect address alignment
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// and to align to size, apply this mask with zero to the address.
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//-------------------------------------------------------------------------
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// THe function return a vector which has width [(SELECT_BITS * 2) -1 : 0]
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// in which the first part contains the mask to check if this address aligned or not
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// second part contains the mast to mask address to align to size
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function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address;
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input [ADDR_W-1:0] address;
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input [SIZE_W-1:0] size; // size is in AXI coding: 001 -> 2 bytes
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integer i;
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reg [SELECT_BITS-1:0] mask_address;
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reg [SELECT_BITS-1:0] check_unaligned; // any bits =1 -> unalgined (except size = 0; 1 byte)
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mask_address = '1;
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check_unaligned = '0;
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for(i = 0; i < SELECT_BITS ; i = i + 1) begin
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if (i < size) begin
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check_unaligned[i] = address[i];
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mask_address[i] = 1'b0;
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end
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end
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mask_select_and_align_address = {check_unaligned,mask_address};
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endfunction
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reg [ADDR_W-1 : 0] in_address;
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reg [ADDR_W-1 : 0] first_address_aligned;
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reg [SIZE_W-1 : 0] in_size;
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reg [(SELECT_BITS*2)-1 : 0] output_masks;
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// Extract information from input data
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assign in_address = in_data[SIZE_W+ADDR_W-1 : SIZE_W];
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assign in_size = in_data[SIZE_W-1 : 0];
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// Generate the masks
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always_comb
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begin
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output_masks = mask_select_and_align_address(in_address, in_size);
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end
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// Align address if needed
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generate
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// SELECT_BITS == 1: input packet has 1 NUMSYMBOLS (1 bytes), it is aligned
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if (SELECT_BITS == 0)
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assign first_address_aligned = in_address;
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else begin
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// SELECT_BITS ==1 :input packet 2 bytes (2 SYMBOLS)
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wire [SELECT_BITS-1 : 0] aligned_address_bits;
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if (SELECT_BITS == 1)
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assign aligned_address_bits = in_address[0] & output_masks[0];
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else
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assign aligned_address_bits = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0];
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assign first_address_aligned = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits};
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end
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endgenerate
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// Increment address base on size, first address keep the same
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generate
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if (INCREMENT_ADDRESS)
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begin
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reg [ADDR_W-1 : 0] increment_address;
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reg [ADDR_W-1 : 0] out_aligned_address_burst;
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reg [ADDR_W-1 : 0] address_burst;
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reg [ADDR_W-1 : 0] base_address;
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reg [9 : 0] number_bytes_transfer;
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reg [ADDR_W-1 : 0] burstwrap_mask;
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reg [ADDR_W-1 : 0] burst_address_high;
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reg [ADDR_W-1 : 0] burst_address_low;
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reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary;
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reg [TYPE_W-1 : 0] in_type;
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//------------------------------------------------
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// Use the extended burstwrap value to split the high (constant) and
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// low (changing) part of the address
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//-----------------------------------------------
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assign in_type = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W];
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assign in_burstwrap_boundary = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W];
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assign burstwrap_mask = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary};
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assign burst_address_high = out_aligned_address_burst & ~burstwrap_mask;
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assign burst_address_low = out_aligned_address_burst;
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assign number_bytes_transfer = bytes_in_transfer(in_size);
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assign write_burst_type = burst_type_decode(in_type);
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always @*
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begin
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if (in_sop)
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begin
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out_aligned_address_burst = in_address;
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base_address = first_address_aligned;
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end
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else
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begin
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out_aligned_address_burst = address_burst;
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base_address = out_aligned_address_burst;
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end
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case (write_burst_type)
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INCR:
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increment_address = base_address + number_bytes_transfer;
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WRAP:
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increment_address = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high;
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FIXED:
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increment_address = out_aligned_address_burst;
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default:
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increment_address = base_address + number_bytes_transfer;
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endcase // case (write_burst_type)
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end // always @ *
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always_ff @(posedge clk, negedge reset)
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begin
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if (!reset)
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begin
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address_burst <= '0;
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end
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else
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begin
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if (in_valid & out_ready)
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address_burst <= increment_address;
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end
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end
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// send data to output with 2 part: [mask_t0_algin][address_aligned_increment]
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assign out_data = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst};
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end // if (INCREMENT_ADDRESS)
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else
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begin
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assign out_data = {output_masks[SELECT_BITS-1 : 0], first_address_aligned};
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end // else: !if(INCREMENT_ADDRESS)
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endgenerate
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endmodule
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