557 lines
22 KiB
Systemverilog
557 lines
22 KiB
Systemverilog
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// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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// --------------------------------------
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// Merlin Master Translator
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//
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// Converts an Avalon-MM master interface into an
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// Avalon-MM "universal" master interface.
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//
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// The universal interface is defined as the superset of ports
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// and parameters that can represent any legal Avalon
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// interface.
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// --------------------------------------
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`timescale 1 ns / 1 ns
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module altera_merlin_master_translator #(
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parameter
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// widths
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AV_ADDRESS_W = 32,
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AV_DATA_W = 32,
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AV_BURSTCOUNT_W = 4,
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AV_BYTEENABLE_W = 4,
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UAV_ADDRESS_W = 38,
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UAV_BURSTCOUNT_W = 10,
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// optional ports
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USE_BURSTCOUNT = 1,
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USE_BEGINBURSTTRANSFER = 0,
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USE_BEGINTRANSFER = 0,
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USE_CHIPSELECT = 0,
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USE_READ = 1,
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USE_READDATAVALID = 1,
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USE_WRITE = 1,
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USE_WAITREQUEST = 1,
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USE_WRITERESPONSE = 0,
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USE_READRESPONSE = 0,
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AV_REGISTERINCOMINGSIGNALS = 0,
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AV_SYMBOLS_PER_WORD = 4,
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AV_ADDRESS_SYMBOLS = 0,
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// must be enabled for a bursting master
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AV_CONSTANT_BURST_BEHAVIOR = 1,
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UAV_CONSTANT_BURST_BEHAVIOR = 0,
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AV_BURSTCOUNT_SYMBOLS = 0,
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AV_LINEWRAPBURSTS = 0
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)(
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input wire clk,
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input wire reset,
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// Universal Avalon Master
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output reg uav_write,
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output reg uav_read,
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output reg [UAV_ADDRESS_W -1 : 0] uav_address,
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output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
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output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
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output wire [AV_DATA_W -1 : 0] uav_writedata,
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output wire uav_lock,
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output wire uav_debugaccess,
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output wire uav_clken,
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input wire [AV_DATA_W -1 : 0] uav_readdata,
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input wire uav_readdatavalid,
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input wire uav_waitrequest,
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input wire [1 : 0] uav_response,
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input wire uav_writeresponsevalid,
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// Avalon-MM Anti-master (slave)
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input reg av_write,
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input reg av_read,
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input wire [AV_ADDRESS_W -1 : 0] av_address,
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input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable,
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input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount,
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input wire [AV_DATA_W -1 : 0] av_writedata,
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input wire av_begintransfer,
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input wire av_beginbursttransfer,
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input wire av_lock,
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input wire av_chipselect,
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input wire av_debugaccess,
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input wire av_clken,
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output wire [AV_DATA_W -1 : 0] av_readdata,
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output wire av_readdatavalid,
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output reg av_waitrequest,
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output reg [1 : 0] av_response,
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output reg av_writeresponsevalid
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);
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localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD);
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localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD));
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localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0;
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localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1;
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localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1;
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localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD;
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localparam BITS_PER_WORD_ADDRESS = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD;
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localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
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localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
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localparam ADDRESS_HIGH = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW);
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localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW);
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function integer flog2;
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input [31:0] depth;
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integer i;
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begin
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i = depth;
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if ( i <= 0 ) flog2 = 0;
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else begin
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for (flog2 = -1; i > 0; flog2 = flog2 + 1)
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i = i >> 1;
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end
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end
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endfunction // flog2
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// ------------------------------------------------------------
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// Calculates the ceil(log2()) of the input val.
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//
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// Limited to a positive 32-bit input value.
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// ------------------------------------------------------------
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function integer clog2;
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input[31:0] val;
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reg[31:0] i;
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begin
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i = 1;
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clog2 = 0;
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while (i < val) begin
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clog2 = clog2 + 1;
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i = i[30:0] << 1;
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end
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end
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endfunction
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function integer pow2;
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input [31:0] toShift;
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begin
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pow2 = 1;
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pow2 = pow2 << toShift;
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end
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endfunction // pow2
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// -------------------------------------------------
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// Assign some constants to appropriately-sized signals to
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// avoid synthesis warnings. This also helps some simulators
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// with their inferred sensitivity lists.
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//
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// The symbols per word calculation here rounds non-power of two
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// symbols to the next highest power of two, which is what we want
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// when calculating the decrementing byte count.
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// -------------------------------------------------
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wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0]));
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wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0];
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reg internal_beginbursttransfer;
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reg internal_begintransfer;
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reg [UAV_ADDRESS_W -1 : 0] uav_address_pre;
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reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount_pre;
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reg uav_read_pre;
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reg uav_write_pre;
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reg read_accepted;
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// -------------------------------------------------
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// Pass through signals that we don't touch
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// -------------------------------------------------
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assign uav_writedata = av_writedata;
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assign uav_byteenable = av_byteenable;
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assign uav_lock = av_lock;
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assign uav_debugaccess = av_debugaccess;
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assign uav_clken = av_clken;
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assign av_readdata = uav_readdata;
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assign av_readdatavalid = uav_readdatavalid;
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// -------------------------------------------------
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// Response signals
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// -------------------------------------------------
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always_comb begin
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if (!USE_READRESPONSE && !USE_WRITERESPONSE)
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av_response = '0;
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else
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av_response = uav_response;
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if (USE_WRITERESPONSE) begin
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av_writeresponsevalid = uav_writeresponsevalid;
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end else begin
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av_writeresponsevalid = '0;
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end
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end
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// -------------------------------------------------
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// Convert byte and word addresses into byte addresses
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// -------------------------------------------------
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always_comb begin
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uav_address_pre = {UAV_ADDRESS_W{1'b0}};
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if (AV_ADDRESS_SYMBOLS)
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uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
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else begin
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uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
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end
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end
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// -------------------------------------------------
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// Convert burstcount into symbol units
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// -------------------------------------------------
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always_comb begin
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uav_burstcount_pre = symbols_per_word; // default to a single transfer
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if (USE_BURSTCOUNT) begin
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uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}};
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if (AV_BURSTCOUNT_SYMBOLS)
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uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
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else begin
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uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
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end
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end
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end
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// -------------------------------------------------
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// This is where we perform the per-transfer address and burstcount
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// calculations that are required by downstream modules.
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// -------------------------------------------------
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reg [UAV_ADDRESS_W -1 : 0] address_register;
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wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register;
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reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint;
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assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0];
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always_comb begin
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uav_address = uav_address_pre;
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uav_burstcount = uav_burstcount_pre;
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if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
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uav_address = address_register;
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uav_burstcount = burstcount_register;
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end
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end
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reg first_burst_stalled;
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reg burst_stalled;
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wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg;
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wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg;
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generate
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if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin
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if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
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assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
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assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
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end
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else begin
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assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
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assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
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end
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end
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else begin
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assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
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assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
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end
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endgenerate
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always @(posedge clk, posedge reset) begin
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if (reset) begin
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address_register <= '0;
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burstcount_register_lint <= '0;
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end else begin
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address_register <= address_register;
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burstcount_register_lint <= burstcount_register_lint;
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if (internal_beginbursttransfer || first_burst_stalled) begin
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if (av_waitrequest) begin
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address_register <= uav_address_pre;
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burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre;
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end else begin
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address_register <= combi_burst_addr_reg;
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burstcount_register_lint <= uav_burstcount_pre - symbols_per_word;
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end
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end else if (internal_begintransfer || burst_stalled) begin
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if (~av_waitrequest) begin
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address_register <= combi_addr_reg;
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burstcount_register_lint <= burstcount_register - symbols_per_word;
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end
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end
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end
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end
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always @(posedge clk, posedge reset) begin
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if (reset) begin
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first_burst_stalled <= 1'b0;
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burst_stalled <= 1'b0;
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end else begin
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if (internal_beginbursttransfer || first_burst_stalled) begin
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if (av_waitrequest) begin
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first_burst_stalled <= 1'b1;
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end else begin
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first_burst_stalled <= 1'b0;
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end
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end else if (internal_begintransfer || burst_stalled) begin
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if (~av_waitrequest) begin
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burst_stalled <= 1'b0;
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end else begin
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burst_stalled <= 1'b1;
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end
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end
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end
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end
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// -------------------------------------------------
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// Waitrequest translation
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// -------------------------------------------------
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always @(posedge clk, posedge reset) begin
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if (reset)
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read_accepted <= 1'b0;
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else begin
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read_accepted <= read_accepted;
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if (read_accepted == 0)
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read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
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else if (read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives
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read_accepted <= 1'b0;
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end
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|
|
end
|
||
|
|
|
||
|
|
reg write_accepted = 0;
|
||
|
|
generate if (AV_REGISTERINCOMINGSIGNALS) begin
|
||
|
|
always @(posedge clk, posedge reset) begin
|
||
|
|
if (reset)
|
||
|
|
write_accepted <= 1'b0;
|
||
|
|
else begin
|
||
|
|
write_accepted <=
|
||
|
|
~av_waitrequest ? 1'b0 :
|
||
|
|
uav_write & ~uav_waitrequest? 1'b1 :
|
||
|
|
write_accepted;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end endgenerate
|
||
|
|
|
||
|
|
always_comb begin
|
||
|
|
av_waitrequest = uav_waitrequest;
|
||
|
|
|
||
|
|
if (USE_READDATAVALID == 0) begin
|
||
|
|
av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
|
||
|
|
end
|
||
|
|
|
||
|
|
if (AV_REGISTERINCOMINGSIGNALS) begin
|
||
|
|
av_waitrequest =
|
||
|
|
uav_read_pre ? ~uav_readdatavalid :
|
||
|
|
uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
|
||
|
|
1'b1;
|
||
|
|
end
|
||
|
|
|
||
|
|
if (USE_WAITREQUEST == 0) begin
|
||
|
|
av_waitrequest = 0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
// -------------------------------------------------
|
||
|
|
// Determine the output read and write signals from
|
||
|
|
// the read/write/chipselect input signals.
|
||
|
|
// -------------------------------------------------
|
||
|
|
always_comb begin
|
||
|
|
uav_write = 1'b0;
|
||
|
|
uav_write_pre = 1'b0;
|
||
|
|
uav_read = 1'b0;
|
||
|
|
uav_read_pre = 1'b0;
|
||
|
|
|
||
|
|
if (!USE_CHIPSELECT) begin
|
||
|
|
if (USE_READ) begin
|
||
|
|
uav_read_pre = av_read;
|
||
|
|
end
|
||
|
|
|
||
|
|
if (USE_WRITE) begin
|
||
|
|
uav_write_pre = av_write;
|
||
|
|
end
|
||
|
|
end else begin
|
||
|
|
if (!USE_WRITE && USE_READ) begin
|
||
|
|
uav_write_pre = av_chipselect & ~av_read;
|
||
|
|
uav_read_pre = av_read;
|
||
|
|
end else if (!USE_READ && USE_WRITE) begin
|
||
|
|
uav_write_pre = av_write;
|
||
|
|
uav_read_pre = av_chipselect & ~av_write;
|
||
|
|
end else if (USE_READ && USE_WRITE) begin
|
||
|
|
uav_write_pre = av_write;
|
||
|
|
uav_read_pre = av_read;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
if (USE_READDATAVALID == 0)
|
||
|
|
uav_read = uav_read_pre & ~read_accepted;
|
||
|
|
else
|
||
|
|
uav_read = uav_read_pre;
|
||
|
|
|
||
|
|
if (AV_REGISTERINCOMINGSIGNALS == 0)
|
||
|
|
uav_write = uav_write_pre;
|
||
|
|
else
|
||
|
|
uav_write = uav_write_pre & ~write_accepted;
|
||
|
|
end
|
||
|
|
|
||
|
|
// -------------------------------------------------
|
||
|
|
// Begintransfer assignment
|
||
|
|
// -------------------------------------------------
|
||
|
|
reg end_begintransfer;
|
||
|
|
|
||
|
|
always_comb begin
|
||
|
|
if (USE_BEGINTRANSFER) begin
|
||
|
|
internal_begintransfer = av_begintransfer;
|
||
|
|
end else begin
|
||
|
|
internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @(posedge clk or posedge reset) begin
|
||
|
|
if (reset) begin
|
||
|
|
end_begintransfer <= 1'b0;
|
||
|
|
end else begin
|
||
|
|
if (internal_begintransfer == 1 && uav_waitrequest)
|
||
|
|
end_begintransfer <= 1'b1;
|
||
|
|
else if (uav_waitrequest)
|
||
|
|
end_begintransfer <= end_begintransfer;
|
||
|
|
else
|
||
|
|
end_begintransfer <= 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
// -------------------------------------------------
|
||
|
|
// Beginbursttransfer assignment
|
||
|
|
// -------------------------------------------------
|
||
|
|
reg end_beginbursttransfer;
|
||
|
|
wire last_burst_transfer_pre;
|
||
|
|
wire last_burst_transfer_reg;
|
||
|
|
wire last_burst_transfer;
|
||
|
|
|
||
|
|
// compare values before the mux to shorten critical path; benchmark before changing
|
||
|
|
assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
|
||
|
|
assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
|
||
|
|
assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
|
||
|
|
|
||
|
|
always_comb begin
|
||
|
|
if (USE_BEGINBURSTTRANSFER) begin
|
||
|
|
internal_beginbursttransfer = av_beginbursttransfer;
|
||
|
|
end else begin
|
||
|
|
internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @(posedge clk or posedge reset) begin
|
||
|
|
if (reset) begin
|
||
|
|
end_beginbursttransfer <= 1'b0;
|
||
|
|
end else begin
|
||
|
|
end_beginbursttransfer <= end_beginbursttransfer;
|
||
|
|
if (last_burst_transfer && internal_begintransfer || uav_read) begin
|
||
|
|
end_beginbursttransfer <= 1'b0;
|
||
|
|
end
|
||
|
|
else if (uav_write && internal_begintransfer) begin
|
||
|
|
end_beginbursttransfer <= 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
// synthesis translate_off
|
||
|
|
|
||
|
|
// ------------------------------------------------
|
||
|
|
// check_1 : for waitrequest signal violation
|
||
|
|
// Ensure that when waitreqeust is asserted, the master is not allowed to change its controls
|
||
|
|
// Exception : begintransfer / beginbursttransfer
|
||
|
|
// : previously not in any transaction (idle)
|
||
|
|
// Note : Not checking clken which is not exactly part of Avalon controls/inputs
|
||
|
|
// : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE
|
||
|
|
// ------------------------------------------------
|
||
|
|
|
||
|
|
reg av_waitrequest_r;
|
||
|
|
reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r;
|
||
|
|
reg [AV_ADDRESS_W-1:0] av_address_r;
|
||
|
|
reg [AV_BYTEENABLE_W-1:0] av_byteenable_r;
|
||
|
|
reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r;
|
||
|
|
reg [AV_DATA_W-1:0] av_writedata_r;
|
||
|
|
|
||
|
|
always @(posedge clk or posedge reset) begin
|
||
|
|
if (reset) begin
|
||
|
|
av_waitrequest_r <= '0;
|
||
|
|
av_write_r <= '0;
|
||
|
|
av_read_r <= '0;
|
||
|
|
av_lock_r <= '0;
|
||
|
|
av_chipselect_r <= '0;
|
||
|
|
av_debugaccess_r <= '0;
|
||
|
|
av_address_r <= '0;
|
||
|
|
av_byteenable_r <= '0;
|
||
|
|
av_burstcount_r <= '0;
|
||
|
|
av_writedata_r <= '0;
|
||
|
|
end else begin
|
||
|
|
av_waitrequest_r <= av_waitrequest;
|
||
|
|
av_write_r <= av_write;
|
||
|
|
av_read_r <= av_read;
|
||
|
|
av_lock_r <= av_lock;
|
||
|
|
av_chipselect_r <= av_chipselect;
|
||
|
|
av_debugaccess_r <= av_debugaccess;
|
||
|
|
av_address_r <= av_address;
|
||
|
|
av_byteenable_r <= av_byteenable;
|
||
|
|
av_burstcount_r <= av_burstcount;
|
||
|
|
av_writedata_r <= av_writedata;
|
||
|
|
|
||
|
|
if (
|
||
|
|
av_waitrequest_r && // When waitrequest is asserted
|
||
|
|
(
|
||
|
|
(av_write != av_write_r) || // Checks that : Input controls/data does not change
|
||
|
|
(av_read != av_read_r) ||
|
||
|
|
(av_lock != av_lock_r) ||
|
||
|
|
(av_debugaccess != av_debugaccess_r) ||
|
||
|
|
(av_address != av_address_r) ||
|
||
|
|
(av_byteenable != av_byteenable_r) ||
|
||
|
|
(av_burstcount != av_burstcount_r)
|
||
|
|
) &&
|
||
|
|
(av_write_r | av_read_r) && // Check only when : previously initiated a write/read
|
||
|
|
(!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused)
|
||
|
|
) begin
|
||
|
|
$display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time());
|
||
|
|
$display("av_address %x --> %x", av_address_r , av_address );
|
||
|
|
$display("av_byteenable %x --> %x", av_byteenable_r , av_byteenable );
|
||
|
|
$display("av_burstcount %x --> %x", av_burstcount_r , av_burstcount );
|
||
|
|
$display("av_writedata %x --> %x", av_writedata_r , av_writedata );
|
||
|
|
$display("av_write %x --> %x", av_write_r , av_write );
|
||
|
|
$display("av_read %x --> %x", av_read_r , av_read );
|
||
|
|
$display("av_lock %x --> %x", av_lock_r , av_lock );
|
||
|
|
$display("av_chipselect %x --> %x", av_chipselect_r , av_chipselect );
|
||
|
|
$display("av_debugaccess %x --> %x", av_debugaccess_r , av_debugaccess );
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
// end check_1
|
||
|
|
|
||
|
|
end
|
||
|
|
|
||
|
|
// synthesis translate_on
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|