169 lines
15 KiB
Coq
169 lines
15 KiB
Coq
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// ddr3_mm_interconnect_1.v
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// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
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// will probably be lost.
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//
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// Generated using ACDS version 15.1 185
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`timescale 1 ps / 1 ps
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module ddr3_mm_interconnect_1 (
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input wire p0_avl_clk_clk, // p0_avl_clk.clk
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input wire dmaster_clk_reset_reset_bridge_in_reset_reset, // dmaster_clk_reset_reset_bridge_in_reset.reset
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input wire dmaster_master_translator_reset_reset_bridge_in_reset_reset, // dmaster_master_translator_reset_reset_bridge_in_reset.reset
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input wire [31:0] dmaster_master_address, // dmaster_master.address
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output wire dmaster_master_waitrequest, // .waitrequest
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input wire [3:0] dmaster_master_byteenable, // .byteenable
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input wire dmaster_master_read, // .read
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output wire [31:0] dmaster_master_readdata, // .readdata
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output wire dmaster_master_readdatavalid, // .readdatavalid
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input wire dmaster_master_write, // .write
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input wire [31:0] dmaster_master_writedata, // .writedata
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output wire [31:0] s0_seq_debug_address, // s0_seq_debug.address
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output wire s0_seq_debug_write, // .write
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output wire s0_seq_debug_read, // .read
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input wire [31:0] s0_seq_debug_readdata, // .readdata
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output wire [31:0] s0_seq_debug_writedata, // .writedata
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output wire [0:0] s0_seq_debug_burstcount, // .burstcount
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output wire [3:0] s0_seq_debug_byteenable, // .byteenable
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input wire s0_seq_debug_readdatavalid, // .readdatavalid
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input wire s0_seq_debug_waitrequest // .waitrequest
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);
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wire dmaster_master_translator_avalon_universal_master_0_waitrequest; // s0_seq_debug_translator:uav_waitrequest -> dmaster_master_translator:uav_waitrequest
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wire [31:0] dmaster_master_translator_avalon_universal_master_0_readdata; // s0_seq_debug_translator:uav_readdata -> dmaster_master_translator:uav_readdata
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wire dmaster_master_translator_avalon_universal_master_0_debugaccess; // dmaster_master_translator:uav_debugaccess -> s0_seq_debug_translator:uav_debugaccess
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wire [31:0] dmaster_master_translator_avalon_universal_master_0_address; // dmaster_master_translator:uav_address -> s0_seq_debug_translator:uav_address
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wire dmaster_master_translator_avalon_universal_master_0_read; // dmaster_master_translator:uav_read -> s0_seq_debug_translator:uav_read
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wire [3:0] dmaster_master_translator_avalon_universal_master_0_byteenable; // dmaster_master_translator:uav_byteenable -> s0_seq_debug_translator:uav_byteenable
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wire dmaster_master_translator_avalon_universal_master_0_readdatavalid; // s0_seq_debug_translator:uav_readdatavalid -> dmaster_master_translator:uav_readdatavalid
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wire dmaster_master_translator_avalon_universal_master_0_lock; // dmaster_master_translator:uav_lock -> s0_seq_debug_translator:uav_lock
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wire dmaster_master_translator_avalon_universal_master_0_write; // dmaster_master_translator:uav_write -> s0_seq_debug_translator:uav_write
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wire [31:0] dmaster_master_translator_avalon_universal_master_0_writedata; // dmaster_master_translator:uav_writedata -> s0_seq_debug_translator:uav_writedata
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wire [2:0] dmaster_master_translator_avalon_universal_master_0_burstcount; // dmaster_master_translator:uav_burstcount -> s0_seq_debug_translator:uav_burstcount
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altera_merlin_master_translator #(
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.AV_ADDRESS_W (32),
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.AV_DATA_W (32),
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.AV_BURSTCOUNT_W (1),
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.AV_BYTEENABLE_W (4),
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.UAV_ADDRESS_W (32),
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.UAV_BURSTCOUNT_W (3),
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.USE_READ (1),
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.USE_WRITE (1),
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.USE_BEGINBURSTTRANSFER (0),
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.USE_BEGINTRANSFER (0),
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.USE_CHIPSELECT (0),
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.USE_BURSTCOUNT (0),
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.USE_READDATAVALID (1),
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.USE_WAITREQUEST (1),
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.USE_READRESPONSE (0),
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.USE_WRITERESPONSE (0),
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.AV_SYMBOLS_PER_WORD (4),
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.AV_ADDRESS_SYMBOLS (1),
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.AV_BURSTCOUNT_SYMBOLS (0),
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.AV_CONSTANT_BURST_BEHAVIOR (0),
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.UAV_CONSTANT_BURST_BEHAVIOR (0),
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.AV_LINEWRAPBURSTS (0),
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.AV_REGISTERINCOMINGSIGNALS (0)
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) dmaster_master_translator (
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.clk (p0_avl_clk_clk), // clk.clk
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.reset (dmaster_master_translator_reset_reset_bridge_in_reset_reset), // reset.reset
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.uav_address (dmaster_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
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.uav_burstcount (dmaster_master_translator_avalon_universal_master_0_burstcount), // .burstcount
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.uav_read (dmaster_master_translator_avalon_universal_master_0_read), // .read
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.uav_write (dmaster_master_translator_avalon_universal_master_0_write), // .write
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.uav_waitrequest (dmaster_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
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.uav_readdatavalid (dmaster_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
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.uav_byteenable (dmaster_master_translator_avalon_universal_master_0_byteenable), // .byteenable
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.uav_readdata (dmaster_master_translator_avalon_universal_master_0_readdata), // .readdata
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.uav_writedata (dmaster_master_translator_avalon_universal_master_0_writedata), // .writedata
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.uav_lock (dmaster_master_translator_avalon_universal_master_0_lock), // .lock
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.uav_debugaccess (dmaster_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
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.av_address (dmaster_master_address), // avalon_anti_master_0.address
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.av_waitrequest (dmaster_master_waitrequest), // .waitrequest
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.av_byteenable (dmaster_master_byteenable), // .byteenable
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.av_read (dmaster_master_read), // .read
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.av_readdata (dmaster_master_readdata), // .readdata
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.av_readdatavalid (dmaster_master_readdatavalid), // .readdatavalid
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.av_write (dmaster_master_write), // .write
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.av_writedata (dmaster_master_writedata), // .writedata
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.av_burstcount (1'b1), // (terminated)
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.av_beginbursttransfer (1'b0), // (terminated)
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.av_begintransfer (1'b0), // (terminated)
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.av_chipselect (1'b0), // (terminated)
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.av_lock (1'b0), // (terminated)
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.av_debugaccess (1'b0), // (terminated)
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.uav_clken (), // (terminated)
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.av_clken (1'b1), // (terminated)
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.uav_response (2'b00), // (terminated)
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.av_response (), // (terminated)
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.uav_writeresponsevalid (1'b0), // (terminated)
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.av_writeresponsevalid () // (terminated)
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);
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altera_merlin_slave_translator #(
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.AV_ADDRESS_W (32),
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.AV_DATA_W (32),
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.UAV_DATA_W (32),
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.AV_BURSTCOUNT_W (1),
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.AV_BYTEENABLE_W (4),
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.UAV_BYTEENABLE_W (4),
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.UAV_ADDRESS_W (32),
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.UAV_BURSTCOUNT_W (3),
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.AV_READLATENCY (0),
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.USE_READDATAVALID (1),
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.USE_WAITREQUEST (1),
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.USE_UAV_CLKEN (0),
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.USE_READRESPONSE (0),
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.USE_WRITERESPONSE (0),
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.AV_SYMBOLS_PER_WORD (4),
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.AV_ADDRESS_SYMBOLS (1),
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.AV_BURSTCOUNT_SYMBOLS (0),
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.AV_CONSTANT_BURST_BEHAVIOR (0),
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.UAV_CONSTANT_BURST_BEHAVIOR (0),
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.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
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.CHIPSELECT_THROUGH_READLATENCY (0),
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.AV_READ_WAIT_CYCLES (1),
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.AV_WRITE_WAIT_CYCLES (0),
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.AV_SETUP_WAIT_CYCLES (0),
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.AV_DATA_HOLD_CYCLES (0)
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) s0_seq_debug_translator (
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.clk (p0_avl_clk_clk), // clk.clk
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.reset (dmaster_master_translator_reset_reset_bridge_in_reset_reset), // reset.reset
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.uav_address (dmaster_master_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
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.uav_burstcount (dmaster_master_translator_avalon_universal_master_0_burstcount), // .burstcount
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.uav_read (dmaster_master_translator_avalon_universal_master_0_read), // .read
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.uav_write (dmaster_master_translator_avalon_universal_master_0_write), // .write
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.uav_waitrequest (dmaster_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
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.uav_readdatavalid (dmaster_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
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.uav_byteenable (dmaster_master_translator_avalon_universal_master_0_byteenable), // .byteenable
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.uav_readdata (dmaster_master_translator_avalon_universal_master_0_readdata), // .readdata
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.uav_writedata (dmaster_master_translator_avalon_universal_master_0_writedata), // .writedata
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.uav_lock (dmaster_master_translator_avalon_universal_master_0_lock), // .lock
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.uav_debugaccess (dmaster_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
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.av_address (s0_seq_debug_address), // avalon_anti_slave_0.address
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.av_write (s0_seq_debug_write), // .write
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.av_read (s0_seq_debug_read), // .read
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.av_readdata (s0_seq_debug_readdata), // .readdata
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.av_writedata (s0_seq_debug_writedata), // .writedata
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.av_burstcount (s0_seq_debug_burstcount), // .burstcount
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.av_byteenable (s0_seq_debug_byteenable), // .byteenable
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.av_readdatavalid (s0_seq_debug_readdatavalid), // .readdatavalid
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.av_waitrequest (s0_seq_debug_waitrequest), // .waitrequest
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.av_begintransfer (), // (terminated)
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.av_beginbursttransfer (), // (terminated)
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.av_writebyteenable (), // (terminated)
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.av_lock (), // (terminated)
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.av_chipselect (), // (terminated)
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.av_clken (), // (terminated)
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.uav_clken (1'b0), // (terminated)
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.av_debugaccess (), // (terminated)
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.av_outputenable (), // (terminated)
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.uav_response (), // (terminated)
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.av_response (2'b00), // (terminated)
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.uav_writeresponsevalid (), // (terminated)
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.av_writeresponsevalid (1'b0) // (terminated)
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);
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endmodule
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