474 lines
17 KiB
Tcl
474 lines
17 KiB
Tcl
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# (C) 2001-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License Subscription
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# Agreement, Altera MegaCore Function License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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####################################################################
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#
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# THIS IS AN AUTO-GENERATED FILE!
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# -------------------------------
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# If you modify this files, all your changes will be lost if you
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# regenerate the core!
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#
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# FILE DESCRIPTION
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# ----------------
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# This file contains the routines to generate the UniPHY memory
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# interface timing report at the end of the compile flow.
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#
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# These routines are only meant to be used in this specific context.
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# Trying to using them in a different context can have unexpected
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# results.
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#############################################################
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# This report_timing script performs the timing analysis for
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# all memory interfaces in the design. In particular, this
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# script will loop over all memory interface cores and
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# instances and will timing analyze a range of paths that
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# are applicable for each instance. These include the
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# timing analysis for the read capture, write, PHY
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# address/command, and resynchronization paths among others.
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#
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# In performing the above timing analysis, the script
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# calls procedures that are found in a separate file (report_timing_core.tcl)
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# that has all the details of the timing analysis, and this
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# file only serves as the top-level timing analysis flow.
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#
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# To reduce data lookups in all the procuedures that perform
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# the individual timing analysis, data that is needed for
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# multiple procedures is lookup up in this file and passed
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# to the various parameters. These data include both values
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# that are applicable over all operating conditions, and those
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# that are applicable to only one operating condition.
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#
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# In addition to the data that is looked up, the script
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# and the underlying procedures use various other data
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# that are stored in TCL sets and include the following:
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#
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# t(.) : Holds the memory timing parameters
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# board(.) : Holds the board skews and propagation delays
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# SSN(.) : Holds the SSN pushout and pullin delays
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# IP(.) : Holds the configuration of the memory interface
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# that was generated
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# ISI(.) : Holds any intersymbol interference when the
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# memory interface is generated in a multirank
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# topology
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# MP(.) : Holds some process variation data for the memory
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# See below for more information
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# pins(.) : Holds the pin names for the memory interface
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#
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#############################################################
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set script_dir [file dirname [info script]]
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#############################################################
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# Memory Specification Process Variation Information
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#############################################################
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# The percentage of the JEDEC specification that is due
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# to process variation
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set MP(DQSQ) 0.65
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set MP(QH_time) 0.55
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set MP(IS) 0.70
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set MP(IH) 0.6
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set MP(DS) 0.60
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set MP(DH) 0.50
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set MP(DSS) 0.60
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set MP(DSH) 0.60
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set MP(DQSS) 0.5
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set MP(WLH) 0.60
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set MP(WLS) 0.70
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set MP(DQSCK) 0.5
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set MP(DQSCK_T) 0.15
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#############################################################
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# Initialize the environment
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#############################################################
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global quartus
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if { ![info exists quartus(nameofexecutable)] || $quartus(nameofexecutable) != "quartus_sta" } {
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post_message -type error "This script must be run from quartus_sta"
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return 1
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}
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if { ! [ is_project_open ] } {
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if { [ llength $quartus(args) ] > 0 } {
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set project_name [lindex $quartus(args) 0]
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project_open -revision [ get_current_revision $project_name ] $project_name
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} else {
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post_message -type error "Missing project_name argument"
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return 1
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}
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}
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#############################################################
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# Some useful functions
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#############################################################
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source "$script_dir/ddr3_p0_timing.tcl"
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source "$script_dir/ddr3_p0_pin_map.tcl"
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source "$script_dir/ddr3_p0_report_timing_core.tcl"
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set family [get_family_string]
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set family [string tolower $family]
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if {$family == "arria ii gx"} {
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set family "arria ii"
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}
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if {$family == "stratix iv gx"} {
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set family "stratix iv"
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}
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if {$family == "stratix v gx"} {
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set family "stratix v"
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}
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if {$family == "stratix v gt"} {
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set family "stratix v"
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}
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if {$family == "hardcopy iv gx"} {
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set family "hardcopy iv"
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}
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#############################################################
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# Load the timing netlist
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#############################################################
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if { ! [ timing_netlist_exist ] } {
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create_timing_netlist
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}
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set opcs [ list "" ]
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set signoff_mode $::quartus(ipc_mode)
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if { [string match "*Analyzer GUI" [get_current_timequest_report_folder]]} {
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read_sdc
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update_timing_netlist
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set script_dir [file dirname [info script]]
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source "$script_dir/ddr3_p0_timing.tcl"
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source "$script_dir/ddr3_p0_pin_map.tcl"
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source "$script_dir/ddr3_p0_report_timing_core.tcl"
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}
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load_package atoms
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read_atom_netlist
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load_package report
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load_report
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if { ! [timing_netlist_exist] } {
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post_message -type error "Timing Netlist has not been created. Run the 'Update Timing Netlist' task first."
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return
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}
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package require ::quartus::ioo
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package require ::quartus::sin
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initialize_ioo
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#############################################################
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# This is the main timing analysis function
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# It performs the timing analysis over all of the
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# various Memory Interface instances and timing corners
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#############################################################
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set mem_if_memtype "ddr3"
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if [ info exists ddr_db ] {
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unset ddr_db
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}
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###############################################
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# This is the main call to the netlist traversal routines
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# that will automatically find all pins and registers required
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# to timing analyze the Core.
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ddr3_p0_initialize_ddr_db ddr_db
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set old_active_clocks [get_active_clocks]
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set_active_clocks [all_clocks]
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# If multiple instances of this core are present in the
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# design they will all be analyzed through the
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# following loop
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set instances [ array names ddr_db ]
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set inst_id 0
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foreach inst $instances {
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if { [ info exists pins ] } {
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# Clean-up stale content
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unset pins
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}
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array set pins $ddr_db($inst)
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set inst_controller [regsub {p0$} $inst "c0"]
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####################################################
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# #
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# Transfer the pin names to a more readable scheme #
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# #
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####################################################
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set dqs_pins $pins(dqs_pins)
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set dqsn_pins $pins(dqsn_pins)
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set q_groups [ list ]
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foreach dq_group $pins(q_groups) {
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set dq_group $dq_group
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lappend q_groups $dq_group
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}
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set all_dq_pins [ join [ join $q_groups ] ]
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set ck_pins $pins(ck_pins)
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set ckn_pins $pins(ckn_pins)
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set add_pins $pins(add_pins)
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set ba_pins $pins(ba_pins)
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set cmd_pins $pins(cmd_pins)
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set ac_pins [ concat $add_pins $ba_pins $cmd_pins ]
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set dm_pins $pins(dm_pins)
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set all_dq_dm_pins [ concat $all_dq_pins $dm_pins ]
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#################################################################################
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# Find some design values and parameters that will used during the timing analysis
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# that do not change accross the operating conditions
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set period $t(CK)
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# Get the number of PLL steps
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set pll_steps "UNDEFINED"
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# Package skew
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[catch {get_max_package_skew} max_package_skew]
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if { ($max_package_skew == "") } {
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set max_package_skew 0
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} else {
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set max_package_skew [expr $max_package_skew / 1000.0]
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}
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# DLL length
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# Arria V DLL Length is always 8
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set dll_length 8
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# DQS_phase offset
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set dqs_phase [ ddr3_p0_get_dqs_phase $dqs_pins ]
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set fitter_run [ddr3_p0_get_io_interface_type [lindex [lindex $pins(q_groups) 0] 0]]
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if {$fitter_run == ""} {
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post_message -type critical_warning "Fitter (quartus_fit) failed or was not run. Run the Fitter (quartus_fit) successfully before running ReportDDR"
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continue
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}
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# Get the interface type (HPAD or VPAD)
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set interface_type [ddr3_p0_get_io_interface_type $all_dq_pins]
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# Treat the VHPAD interface as the same as a HPAD interface
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if {($interface_type == "VHPAD") || ($interface_type == "HYBRID")} {
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set interface_type "HPAD"
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}
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# Get the IO standard which helps us determine the Memory type
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set io_std [ddr3_p0_get_io_standard [lindex $dqs_pins 0]]
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if {$interface_type == "" || $interface_type == "UNKNOWN" || $io_std == "" || $io_std == "UNKNOWN"} {
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set result 0
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}
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# Get some of the FPGA jitter and DCD specs
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# When not specified all jitter values are peak-to-peak jitters in ns
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set tJITper [expr [get_micro_node_delay -micro MEM_CK_PERIOD_JITTER -parameters [list IO PHY_SHORT] -period $period]/1000.0]
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set tJITdty [expr [get_micro_node_delay -micro MEM_CK_DC_JITTER -parameters [list IO PHY_SHORT]]/1000.0]
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# DCD value that is looked up is in %, and thus needs to be divided by 100
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set tDCD [expr [get_micro_node_delay -micro MEM_CK_DCD -parameters [list IO PHY_SHORT]]/100.0]
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# This is the peak-to-peak jitter on the whole DQ-DQS read capture path
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set DQSpathjitter [expr [get_micro_node_delay -micro DQDQS_JITTER -parameters [list IO] -in_fitter]/1000.0]
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# This is the proportion of the DQ-DQS read capture path jitter that applies to setup (looed up value is in %, and thus needs to be divided by 100)
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set DQSpathjitter_setup_prop [expr [get_micro_node_delay -micro DQDQS_JITTER_DIVISION -parameters [list IO] -in_fitter]/100.0]
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set fname ""
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set fbasename ""
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if {[llength $instances] <= 1} {
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set fbasename "${::GLOBAL_ddr3_p0_corename}"
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} else {
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set fbasename "${::GLOBAL_ddr3_p0_corename}_${inst_id}"
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}
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set fname "${fbasename}_summary.csv"
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#################################################################################
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# Now loop the timing analysis over the various operating conditions
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set summary [list]
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foreach opc $opcs {
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if {$opc != "" } {
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set_operating_conditions $opc
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update_timing_netlist
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}
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set opcname [get_operating_conditions_info [get_operating_conditions] -display_name]
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set opcname [string trim $opcname]
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set model_corner [ddr3_p0_get_model_corner]
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initialize_sin -model [lindex $model_corner 0] -corner [lindex $model_corner 1]
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global assumptions_cache
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set in_gui [regexp "TimeQuest Timing Analyzer GUI" [get_current_timequest_report_folder]]
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if {!$in_gui && [array exists assumptions_cache] && [info exists assumptions_cache(${::GLOBAL_ddr3_p0_corename}-$inst)] } {
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set assumptions_valid $assumptions_cache(${::GLOBAL_ddr3_p0_corename}-$inst)
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if {!$assumptions_valid} {
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post_message -type critical_warning "Read Capture and Write timing analyses may not be valid due to violated timing model assumptions"
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post_message -type critical_warning "See violated timing model assumptions in previous timing analysis above"
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}
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} else {
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set assumptions_valid [ddr3_p0_verify_flexible_timing_assumptions $inst pins $mem_if_memtype]
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set assumptions_cache(${::GLOBAL_ddr3_p0_corename}-$inst) $assumptions_valid
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}
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#######################################
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# Determine parameters and values that are valid only for this operating condition
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set total_max_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {TOTAL_SCALE_FACTOR} -parameters {IO}]
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set total_min_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {TOTAL_SCALE_FACTOR} -parameters {IO MIN}]
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set scale_factors(total) [expr $total_max_scale_factor - $total_min_scale_factor]
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set odv_max_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {ODV_SCALE_FACTOR} -parameters {IO}]
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set odv_min_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {ODV_SCALE_FACTOR} -parameters {IO MIN}]
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set scale_factors(odv) [expr $odv_max_scale_factor - $odv_min_scale_factor]
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set eol_max_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {EOL_SCALE_FACTOR} -parameters {IO}]
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set eol_min_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {EOL_SCALE_FACTOR} -parameters {IO MIN}]
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set scale_factors(eol) [expr $eol_max_scale_factor - $eol_min_scale_factor]
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set emif_max_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {MEM_INTERFACE_SCALE_FACTOR} -parameters {IO}]
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set emif_min_scale_factor [get_float_table_node_delay -src {SCALE_FACTOR} -dst {MEM_INTERFACE_SCALE_FACTOR} -parameters {IO MIN}]
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set scale_factors(emif) [expr $emif_max_scale_factor - $emif_min_scale_factor]
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|
|
|
||
|
|
#######################################
|
||
|
|
# Write Analysis
|
||
|
|
|
||
|
|
ddr3_p0_perform_flexible_write_launch_timing_analysis $opcs $opcname $inst $family scale_factors $interface_type $max_package_skew $dll_length $period pins t summary MP IP board
|
||
|
|
|
||
|
|
#######################################
|
||
|
|
# Read Analysis
|
||
|
|
|
||
|
|
ddr3_p0_perform_flexible_read_capture_timing_analysis $opcs $opcname $inst $family scale_factors $io_std $interface_type $max_package_skew $dqs_phase $period $all_dq_pins pins t summary MP IP board fpga
|
||
|
|
|
||
|
|
#######################################
|
||
|
|
# PHY and Address/command Analyses
|
||
|
|
|
||
|
|
ddr3_p0_perform_ac_analyses $opcs $opcname $inst scale_factors pins t summary IP
|
||
|
|
ddr3_p0_perform_phy_analyses $opcs $opcname $inst $inst_controller pins t summary IP
|
||
|
|
|
||
|
|
|
||
|
|
#######################################
|
||
|
|
# Bus Turnaround Time Analysis
|
||
|
|
ddr3_p0_perform_flexible_bus_turnaround_time_analysis $opcs $opcname $inst $family $period $dll_length $interface_type $tJITper $tJITdty $tDCD $pll_steps pins t summary MP IP SSN board ISI
|
||
|
|
|
||
|
|
|
||
|
|
#######################################
|
||
|
|
# Postamble analysis
|
||
|
|
ddr3_p0_perform_flexible_postamble_timing_analysis $opcs $opcname $inst scale_factors $family $period $dll_length $interface_type $tJITper $tJITdty $tDCD $DQSpathjitter pins t summary MP IP SSN board ISI
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
#################################################
|
||
|
|
# Now perform analysis of some of the calibrated paths that consider
|
||
|
|
# Worst-case conditions
|
||
|
|
|
||
|
|
set opcname "All Conditions"
|
||
|
|
|
||
|
|
#######################################
|
||
|
|
# Print out the Summary Panel for this instance
|
||
|
|
|
||
|
|
set summary [lsort -command ddr3_p0_sort_proc $summary]
|
||
|
|
|
||
|
|
set f -1
|
||
|
|
if { [ddr3_p0_get_operating_conditions_number] == 0 } {
|
||
|
|
set f [open $fname w]
|
||
|
|
|
||
|
|
puts $f "Core: ${::GLOBAL_ddr3_p0_corename} - Instance: $inst"
|
||
|
|
puts $f "Path, Setup Margin, Hold Margin"
|
||
|
|
} else {
|
||
|
|
set f [open $fname a]
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
post_message -type info "Core: ${::GLOBAL_ddr3_p0_corename} - Instance: $inst"
|
||
|
|
post_message -type info " setup hold"
|
||
|
|
set panel_name "$inst"
|
||
|
|
set root_folder_name [get_current_timequest_report_folder]
|
||
|
|
if { ! [string match "${root_folder_name}*" $panel_name] } {
|
||
|
|
set panel_name "${root_folder_name}||$panel_name"
|
||
|
|
}
|
||
|
|
# Create the root if it doesn't yet exist
|
||
|
|
if {[get_report_panel_id $root_folder_name] == -1} {
|
||
|
|
set panel_id [create_report_panel -folder $root_folder_name]
|
||
|
|
}
|
||
|
|
# Delete any pre-existing summary panel
|
||
|
|
set panel_id [get_report_panel_id $panel_name]
|
||
|
|
if {$panel_id != -1} {
|
||
|
|
delete_report_panel -id $panel_id
|
||
|
|
}
|
||
|
|
|
||
|
|
# Create summary panel
|
||
|
|
set total_failures 0
|
||
|
|
set rows [list]
|
||
|
|
lappend rows "add_row_to_table -id \$panel_id \[list \"Path\" \"Operating Condition\" \"Setup Slack\" \"Hold Slack\"\]"
|
||
|
|
foreach summary_line $summary {
|
||
|
|
foreach {corner order path su hold num_su num_hold} $summary_line { }
|
||
|
|
if {($num_su == 0) || ([string trim $su] == "")} {
|
||
|
|
set su "--"
|
||
|
|
}
|
||
|
|
if {($num_hold == 0) || ([string trim $hold] == "")} {
|
||
|
|
set hold "--"
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
if { ($su != "--" && $su < 0) || ($hold != "--" && $hold < 0) } {
|
||
|
|
incr total_failures
|
||
|
|
set type warning
|
||
|
|
set offset 50
|
||
|
|
} else {
|
||
|
|
set type info
|
||
|
|
set offset 53
|
||
|
|
}
|
||
|
|
if {$su != "--"} {
|
||
|
|
set su [ ddr3_p0_round_3dp $su]
|
||
|
|
}
|
||
|
|
if {$hold != "--"} {
|
||
|
|
set hold [ ddr3_p0_round_3dp $hold]
|
||
|
|
}
|
||
|
|
post_message -type $type [format "%-${offset}s | %6s %6s" $path $su $hold]
|
||
|
|
puts $f [format "\"%s\",%s,%s" $path $su $hold]
|
||
|
|
set fg_colours [list black black]
|
||
|
|
if { $su != "--" && $su < 0 } {
|
||
|
|
lappend fg_colours red
|
||
|
|
} else {
|
||
|
|
lappend fg_colours black
|
||
|
|
}
|
||
|
|
|
||
|
|
if { $hold != "" && $hold < 0 } {
|
||
|
|
lappend fg_colours red
|
||
|
|
} else {
|
||
|
|
lappend fg_colours black
|
||
|
|
}
|
||
|
|
lappend rows "add_row_to_table -id \$panel_id -fcolors \"$fg_colours\" \[list \"$path\" \"$corner\" \"$su\" \"$hold\"\]"
|
||
|
|
}
|
||
|
|
close $f
|
||
|
|
if {$total_failures > 0} {
|
||
|
|
post_message -type critical_warning "DDR Timing requirements not met"
|
||
|
|
set panel_id [create_report_panel -table $panel_name -color red]
|
||
|
|
} else {
|
||
|
|
set panel_id [create_report_panel -table $panel_name]
|
||
|
|
}
|
||
|
|
foreach row $rows {
|
||
|
|
eval $row
|
||
|
|
}
|
||
|
|
|
||
|
|
write_timing_report
|
||
|
|
|
||
|
|
|
||
|
|
incr inst_id
|
||
|
|
}
|
||
|
|
|
||
|
|
set_active_clocks $old_active_clocks
|
||
|
|
uninitialize_sin
|
||
|
|
uninitialize_ioo
|