59 lines
1.6 KiB
Systemverilog
59 lines
1.6 KiB
Systemverilog
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// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/15.1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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// -------------------------------------------------------
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// Altera IRQ Mapper
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//
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// Parameters
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// NUM_RCVRS : 0
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// SENDER_IRW_WIDTH : 32
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// IRQ_MAP :
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//
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// -------------------------------------------------------
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`timescale 1 ns / 1 ns
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module ddr3_s0_irq_mapper
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(
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// -------------------
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// Clock & Reset
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// -------------------
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input clk,
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input reset,
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// -------------------
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// IRQ Receivers
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// -------------------
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// -------------------
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// Command Source (Output)
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// -------------------
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output reg [31 : 0] sender_irq
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);
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initial sender_irq = 0;
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always @* begin
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sender_irq = 0;
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end
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endmodule
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