73 lines
2.7 KiB
Coq
73 lines
2.7 KiB
Coq
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// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// --------------------------------------------------------------------------------
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//| Avalon ST Idle Inserter
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// --------------------------------------------------------------------------------
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`timescale 1ns / 100ps
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module altera_avalon_st_idle_inserter (
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// Interface: clk
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input clk,
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input reset_n,
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// Interface: ST in
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output reg in_ready,
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input in_valid,
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input [7: 0] in_data,
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// Interface: ST out
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input out_ready,
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output reg out_valid,
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output reg [7: 0] out_data
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);
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// ---------------------------------------------------------------------
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//| Signal Declarations
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// ---------------------------------------------------------------------
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reg received_esc;
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wire escape_char, idle_char;
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// ---------------------------------------------------------------------
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//| Thingofamagick
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// ---------------------------------------------------------------------
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assign idle_char = (in_data == 8'h4a);
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assign escape_char = (in_data == 8'h4d);
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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received_esc <= 0;
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end else begin
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if (in_valid & out_ready) begin
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if ((idle_char | escape_char) & ~received_esc & out_ready) begin
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received_esc <= 1;
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end else begin
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received_esc <= 0;
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end
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end
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end
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end
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always @* begin
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//we are always valid
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out_valid = 1'b1;
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in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
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out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
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(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
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(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
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in_data; //send data
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end
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endmodule
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