483 lines
16 KiB
Systemverilog
483 lines
16 KiB
Systemverilog
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// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// $Id: //acds/rel/15.1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
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// $Revision: #1 $
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// $Date: 2015/08/09 $
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// $Author: swbranch $
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// -------------------------------------
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// Merlin Slave Translator
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//
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// Translates Universal Avalon MM Slave
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// to any Avalon MM Slave
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// -------------------------------------
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//
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//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
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//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
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//The key feature here is that no same cycle turnaround data is processed through the fabric.
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//import avalon_utilities_pkg::*;
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`timescale 1 ns / 1 ns
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module altera_merlin_slave_translator #(
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parameter
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//Widths
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AV_ADDRESS_W = 32,
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AV_DATA_W = 32,
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AV_BURSTCOUNT_W = 4,
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AV_BYTEENABLE_W = 4,
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UAV_BYTEENABLE_W = 4,
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//Read Latency
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AV_READLATENCY = 1,
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//Timing
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AV_READ_WAIT_CYCLES = 0,
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AV_WRITE_WAIT_CYCLES = 0,
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AV_SETUP_WAIT_CYCLES = 0,
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AV_DATA_HOLD_CYCLES = 0,
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//Optional Port Declarations
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USE_READDATAVALID = 1,
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USE_WAITREQUEST = 1,
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USE_READRESPONSE = 0,
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USE_WRITERESPONSE = 0,
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//Variable Addressing
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AV_SYMBOLS_PER_WORD = 4,
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AV_ADDRESS_SYMBOLS = 0,
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AV_BURSTCOUNT_SYMBOLS = 0,
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BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
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UAV_ADDRESS_W = 38,
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UAV_BURSTCOUNT_W = 10,
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UAV_DATA_W = 32,
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AV_CONSTANT_BURST_BEHAVIOR = 0,
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UAV_CONSTANT_BURST_BEHAVIOR = 0,
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CHIPSELECT_THROUGH_READLATENCY = 0,
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// Tightly-Coupled Options
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USE_UAV_CLKEN = 0,
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AV_REQUIRE_UNALIGNED_ADDRESSES = 0
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) (
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// -------------------
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// Clock & Reset
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// -------------------
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input wire clk,
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input wire reset,
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// -------------------
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// Universal Avalon Slave
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// -------------------
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input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
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input wire [UAV_DATA_W - 1 : 0] uav_writedata,
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input wire uav_write,
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input wire uav_read,
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input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
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input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
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input wire uav_lock,
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input wire uav_debugaccess,
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input wire uav_clken,
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output logic uav_readdatavalid,
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output logic uav_waitrequest,
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output logic [UAV_DATA_W - 1 : 0] uav_readdata,
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output logic [1:0] uav_response,
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// input wire uav_writeresponserequest,
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output logic uav_writeresponsevalid,
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// -------------------
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// Customizable Avalon Master
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// -------------------
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output logic [AV_ADDRESS_W - 1 : 0] av_address,
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output logic [AV_DATA_W - 1 : 0] av_writedata,
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output logic av_write,
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output logic av_read,
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output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
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output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
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output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
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output logic av_begintransfer,
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output wire av_chipselect,
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output logic av_beginbursttransfer,
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output logic av_lock,
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output wire av_clken,
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output wire av_debugaccess,
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output wire av_outputenable,
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input logic [AV_DATA_W - 1 : 0] av_readdata,
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input logic av_readdatavalid,
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input logic av_waitrequest,
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input logic [1:0] av_response,
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// output logic av_writeresponserequest,
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input wire av_writeresponsevalid
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);
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function integer clog2_plusone;
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input [31:0] Depth;
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integer i;
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begin
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i = Depth;
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for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
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i = i >> 1;
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end
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endfunction
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function integer max;
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//returns the larger of two passed arguments
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input [31:0] one;
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input [31:0] two;
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if(one > two)
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max=one;
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else
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max=two;
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endfunction // int
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localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
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localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
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localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
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localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
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localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
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localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
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localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
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AV_ADDRESS_W :
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UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
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localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
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AV_BURSTCOUNT_W :
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UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
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localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
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// Calculate the symbols per word as the power of 2 extended symbols per word
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wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
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wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
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// +--------------------------------
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// |Backwards Compatibility Signals
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// +--------------------------------
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assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
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assign av_debugaccess = uav_debugaccess;
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// +-------------------
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// |Passthru Signals
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// +-------------------
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reg [1 : 0] av_response_delayed;
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always @(posedge clk, posedge reset) begin
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if (reset) begin
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av_response_delayed <= 2'b0;
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end else begin
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av_response_delayed <= av_response;
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end
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end
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always_comb
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begin
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if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
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uav_response = '0;
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end else begin
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if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
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uav_response = av_response;
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end else begin
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uav_response = av_response_delayed;
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end
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end
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end
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// assign av_writeresponserequest = uav_writeresponserequest;
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assign uav_writeresponsevalid = av_writeresponsevalid;
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//-------------------------
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//Writedata and Byteenable
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//-------------------------
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always@* begin
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av_byteenable = '0;
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av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
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end
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always@* begin
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av_writedata = '0;
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av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
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end
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// +-------------------
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// |Calculated Signals
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// +-------------------
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logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
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function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
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input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
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for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
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if(byteenable[i] == 1) begin
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return i;
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end
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end
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return '0;
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endfunction
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reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
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reg [AV_ADDRESS_W - 1 : 0] address_reg;
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always@(posedge clk, posedge reset) begin
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if(reset) begin
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burstcount_reg <= '0;
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address_reg <= '0;
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end else begin
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burstcount_reg <= burstcount_reg;
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address_reg <= address_reg;
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if(av_beginbursttransfer) begin
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burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
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address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
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end
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end
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end
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logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
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always@* begin
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if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
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temp_wire = decode_byteenable(uav_byteenable);
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real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
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end else begin
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real_uav_address = uav_address;
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end
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av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
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if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
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av_address = address_reg;
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end
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always@* begin
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av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
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if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
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av_burstcount = burstcount_reg;
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end
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always@* begin
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av_lock = uav_lock;
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end
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// -------------------
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// Writebyteenable Assignment
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// -------------------
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always@* begin
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av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
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end
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// -------------------
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// Waitrequest Assignment
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// -------------------
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reg av_waitrequest_generated;
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reg av_waitrequest_generated_read;
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reg av_waitrequest_generated_write;
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reg waitrequest_reset_override;
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reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
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always@(posedge reset, posedge clk) begin
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if(reset) begin
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wait_latency_counter <= '0;
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waitrequest_reset_override <= 1'h1;
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end else begin
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waitrequest_reset_override <= 1'h0;
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wait_latency_counter <= '0;
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if( ~uav_waitrequest | waitrequest_reset_override )
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wait_latency_counter <= '0;
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else if( uav_read | uav_write )
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wait_latency_counter <= wait_latency_counter + 1'h1;
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end
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end
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always @* begin
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av_read = uav_read;
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av_write = uav_write;
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av_waitrequest_generated = 1'h1;
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av_waitrequest_generated_read = 1'h1;
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av_waitrequest_generated_write = 1'h1;
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if(LOG2_OF_LATENCY_SUM == 1)
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av_waitrequest_generated = 0;
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if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
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av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
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av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
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av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
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av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
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if(uav_write)
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av_waitrequest_generated = av_waitrequest_generated_write;
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else
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av_waitrequest_generated = av_waitrequest_generated_read;
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end
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if(USE_WAITREQUEST) begin
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uav_waitrequest = av_waitrequest;
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end else begin
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uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
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end
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end
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// --------------
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// Readdata Assignment
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// --------------
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reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
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always@(posedge clk, posedge reset) begin
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if(reset)
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av_readdata_pre <= 'b0;
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else
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av_readdata_pre <= av_readdata;
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end
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|
|
||
|
|
always@* begin
|
||
|
|
uav_readdata = {UAV_DATA_W{1'b0}};
|
||
|
|
if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
|
||
|
|
uav_readdata[AV_DATA_W-1:0] = av_readdata;
|
||
|
|
end else begin
|
||
|
|
uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
// -------------------
|
||
|
|
// Readdatavalid Assigment
|
||
|
|
// -------------------
|
||
|
|
reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
|
||
|
|
reg top_read_latency_shift_reg;
|
||
|
|
|
||
|
|
always@* begin
|
||
|
|
uav_readdatavalid=top_read_latency_shift_reg;
|
||
|
|
if(USE_READDATAVALID) begin
|
||
|
|
uav_readdatavalid = av_readdatavalid;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always@* begin
|
||
|
|
top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
|
||
|
|
if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
|
||
|
|
top_read_latency_shift_reg=read_latency_shift_reg;
|
||
|
|
end
|
||
|
|
if (AV_READLATENCY > 1) begin
|
||
|
|
top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always@(posedge reset, posedge clk) begin
|
||
|
|
if (reset) begin
|
||
|
|
read_latency_shift_reg <= '0;
|
||
|
|
end else if (av_clken) begin
|
||
|
|
read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
|
||
|
|
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
|
||
|
|
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
// ------------
|
||
|
|
// Chipselect and OutputEnable
|
||
|
|
// ------------
|
||
|
|
reg av_chipselect_pre;
|
||
|
|
wire cs_extension;
|
||
|
|
reg av_outputenable_pre;
|
||
|
|
|
||
|
|
assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
|
||
|
|
assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
|
||
|
|
assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
|
||
|
|
|
||
|
|
always@(posedge reset, posedge clk) begin
|
||
|
|
if(reset)
|
||
|
|
av_outputenable_pre <= 1'b0;
|
||
|
|
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
|
||
|
|
av_outputenable_pre <= 0;
|
||
|
|
else
|
||
|
|
av_outputenable_pre <= cs_extension | uav_read;
|
||
|
|
end
|
||
|
|
|
||
|
|
always@(posedge reset, posedge clk) begin
|
||
|
|
if(reset) begin
|
||
|
|
av_chipselect_pre <= 1'b0;
|
||
|
|
end else begin
|
||
|
|
av_chipselect_pre <= 1'b0;
|
||
|
|
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
|
||
|
|
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
|
||
|
|
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
|
||
|
|
if(uav_read) begin
|
||
|
|
av_chipselect_pre <= 1'b1;
|
||
|
|
end else if(cs_extension == 1) begin
|
||
|
|
av_chipselect_pre <= 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
// -------------------
|
||
|
|
// Begintransfer Assigment
|
||
|
|
// -------------------
|
||
|
|
reg end_begintransfer;
|
||
|
|
|
||
|
|
always@* begin
|
||
|
|
av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
|
||
|
|
end
|
||
|
|
|
||
|
|
always@ ( posedge clk or posedge reset ) begin
|
||
|
|
if(reset) begin
|
||
|
|
end_begintransfer <= 1'b0;
|
||
|
|
end else begin
|
||
|
|
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
|
||
|
|
end_begintransfer <= 1'b1;
|
||
|
|
else if(uav_waitrequest)
|
||
|
|
end_begintransfer <= end_begintransfer;
|
||
|
|
else
|
||
|
|
end_begintransfer <= 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
// -------------------
|
||
|
|
// Beginbursttransfer Assigment
|
||
|
|
// -------------------
|
||
|
|
reg end_beginbursttransfer;
|
||
|
|
reg in_transfer;
|
||
|
|
|
||
|
|
always@* begin
|
||
|
|
av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
|
||
|
|
end
|
||
|
|
|
||
|
|
always@ ( posedge clk or posedge reset ) begin
|
||
|
|
if(reset) begin
|
||
|
|
end_beginbursttransfer <= 1'b0;
|
||
|
|
in_transfer <= 1'b0;
|
||
|
|
end else begin
|
||
|
|
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
|
||
|
|
if(uav_write && uav_burstcount == symbols_per_word)
|
||
|
|
in_transfer <=1'b0;
|
||
|
|
else if(uav_write)
|
||
|
|
in_transfer <=1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|