355 lines
21 KiB
Coq
355 lines
21 KiB
Coq
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// ddr3_dmaster.v
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// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
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// will probably be lost.
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//
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// Generated using ACDS version 15.1 185
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`timescale 1 ps / 1 ps
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module ddr3_dmaster #(
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parameter USE_PLI = 0,
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parameter PLI_PORT = 50000,
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parameter FIFO_DEPTHS = 2
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) (
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input wire clk_clk, // clk.clk
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input wire clk_reset_reset, // clk_reset.reset
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output wire [31:0] master_address, // master.address
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input wire [31:0] master_readdata, // .readdata
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output wire master_read, // .read
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output wire master_write, // .write
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output wire [31:0] master_writedata, // .writedata
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input wire master_waitrequest, // .waitrequest
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input wire master_readdatavalid, // .readdatavalid
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output wire [3:0] master_byteenable, // .byteenable
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output wire master_reset_reset // master_reset.reset
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);
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wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
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wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
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wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
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wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
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wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
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wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
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wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
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wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
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wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
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wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
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wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
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wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
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wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
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wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
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wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
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wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
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wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
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wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
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wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
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wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
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wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
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wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
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wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
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wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
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wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
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wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
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wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
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wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
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wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
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wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
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wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
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wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
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wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
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wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
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generate
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// If any of the display statements (or deliberately broken
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// instantiations) within this generate block triggers then this module
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// has been instantiated this module with a set of parameters different
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// from those it was generated for. This will usually result in a
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// non-functioning system.
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if (USE_PLI != 0)
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begin
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initial begin
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$display("Generated module instantiated with wrong parameters");
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$stop;
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end
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instantiated_with_wrong_parameters_error_see_comment_above
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use_pli_check ( .error(1'b1) );
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end
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if (PLI_PORT != 50000)
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begin
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initial begin
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$display("Generated module instantiated with wrong parameters");
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$stop;
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end
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instantiated_with_wrong_parameters_error_see_comment_above
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pli_port_check ( .error(1'b1) );
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end
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if (FIFO_DEPTHS != 2)
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begin
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initial begin
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$display("Generated module instantiated with wrong parameters");
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$stop;
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end
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instantiated_with_wrong_parameters_error_see_comment_above
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fifo_depths_check ( .error(1'b1) );
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end
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endgenerate
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altera_avalon_st_jtag_interface #(
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.PURPOSE (1),
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.UPSTREAM_FIFO_SIZE (0),
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.DOWNSTREAM_FIFO_SIZE (64),
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.MGMT_CHANNEL_WIDTH (-1),
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.EXPORT_JTAG (0),
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.USE_PLI (0),
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.PLI_PORT (50000)
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) jtag_phy_embedded_in_jtag_master (
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.clk (clk_clk), // clock.clk
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.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
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.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
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.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
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.sink_data (p2b_out_bytes_stream_data), // sink.data
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.sink_valid (p2b_out_bytes_stream_valid), // .valid
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.sink_ready (p2b_out_bytes_stream_ready), // .ready
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.resetrequest (master_reset_reset), // resetrequest.reset
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.source_ready (1'b1), // (terminated)
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.mgmt_valid (), // (terminated)
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.mgmt_channel (), // (terminated)
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.mgmt_data (), // (terminated)
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.jtag_tck (1'b0), // (terminated)
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.jtag_tms (1'b0), // (terminated)
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.jtag_tdi (1'b0), // (terminated)
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.jtag_tdo (), // (terminated)
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.jtag_ena (1'b0), // (terminated)
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.jtag_usr1 (1'b0), // (terminated)
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.jtag_clr (1'b0), // (terminated)
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.jtag_clrn (1'b0), // (terminated)
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.jtag_state_tlr (1'b0), // (terminated)
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.jtag_state_rti (1'b0), // (terminated)
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.jtag_state_sdrs (1'b0), // (terminated)
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.jtag_state_cdr (1'b0), // (terminated)
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.jtag_state_sdr (1'b0), // (terminated)
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.jtag_state_e1dr (1'b0), // (terminated)
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.jtag_state_pdr (1'b0), // (terminated)
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.jtag_state_e2dr (1'b0), // (terminated)
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.jtag_state_udr (1'b0), // (terminated)
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.jtag_state_sirs (1'b0), // (terminated)
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.jtag_state_cir (1'b0), // (terminated)
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.jtag_state_sir (1'b0), // (terminated)
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.jtag_state_e1ir (1'b0), // (terminated)
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.jtag_state_pir (1'b0), // (terminated)
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.jtag_state_e2ir (1'b0), // (terminated)
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.jtag_state_uir (1'b0), // (terminated)
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.jtag_ir_in (3'b000), // (terminated)
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.jtag_irq (), // (terminated)
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.jtag_ir_out () // (terminated)
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);
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ddr3_dmaster_timing_adt timing_adt (
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.clk (clk_clk), // clk.clk
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.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
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.in_data (jtag_phy_embedded_in_jtag_master_src_data), // in.data
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.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
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.out_data (timing_adt_out_data), // out.data
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.out_valid (timing_adt_out_valid), // .valid
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.out_ready (timing_adt_out_ready) // .ready
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);
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altera_avalon_sc_fifo #(
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.SYMBOLS_PER_BEAT (1),
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.BITS_PER_SYMBOL (8),
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.FIFO_DEPTH (64),
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.CHANNEL_WIDTH (0),
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.ERROR_WIDTH (0),
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.USE_PACKETS (0),
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.USE_FILL_LEVEL (0),
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.EMPTY_LATENCY (3),
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.USE_MEMORY_BLOCKS (1),
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.USE_STORE_FORWARD (0),
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.USE_ALMOST_FULL_IF (0),
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.USE_ALMOST_EMPTY_IF (0)
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) fifo (
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.clk (clk_clk), // clk.clk
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.reset (rst_controller_reset_out_reset), // clk_reset.reset
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.in_data (timing_adt_out_data), // in.data
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.in_valid (timing_adt_out_valid), // .valid
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.in_ready (timing_adt_out_ready), // .ready
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.out_data (fifo_out_data), // out.data
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.out_valid (fifo_out_valid), // .valid
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.out_ready (fifo_out_ready), // .ready
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.csr_address (2'b00), // (terminated)
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.csr_read (1'b0), // (terminated)
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.csr_write (1'b0), // (terminated)
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.csr_readdata (), // (terminated)
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.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
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.almost_full_data (), // (terminated)
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.almost_empty_data (), // (terminated)
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.in_startofpacket (1'b0), // (terminated)
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.in_endofpacket (1'b0), // (terminated)
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.out_startofpacket (), // (terminated)
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.out_endofpacket (), // (terminated)
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.in_empty (1'b0), // (terminated)
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.out_empty (), // (terminated)
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.in_error (1'b0), // (terminated)
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.out_error (), // (terminated)
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.in_channel (1'b0), // (terminated)
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.out_channel () // (terminated)
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);
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altera_avalon_st_bytes_to_packets #(
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.CHANNEL_WIDTH (8),
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.ENCODING (0)
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) b2p (
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.clk (clk_clk), // clk.clk
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.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
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.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
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.out_ready (b2p_out_packets_stream_ready), // .ready
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.out_valid (b2p_out_packets_stream_valid), // .valid
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.out_data (b2p_out_packets_stream_data), // .data
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.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
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.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
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.in_ready (fifo_out_ready), // in_bytes_stream.ready
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.in_valid (fifo_out_valid), // .valid
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.in_data (fifo_out_data) // .data
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);
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altera_avalon_st_packets_to_bytes #(
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.CHANNEL_WIDTH (8),
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.ENCODING (0)
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) p2b (
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.clk (clk_clk), // clk.clk
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.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
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.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
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.in_valid (p2b_adapter_out_valid), // .valid
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.in_data (p2b_adapter_out_data), // .data
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.in_channel (p2b_adapter_out_channel), // .channel
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.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
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.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
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.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
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.out_valid (p2b_out_bytes_stream_valid), // .valid
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.out_data (p2b_out_bytes_stream_data) // .data
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);
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altera_avalon_packets_to_master #(
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.FAST_VER (0),
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.FIFO_DEPTHS (2),
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.FIFO_WIDTHU (1)
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) transacto (
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.clk (clk_clk), // clk.clk
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.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
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.out_ready (transacto_out_stream_ready), // out_stream.ready
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.out_valid (transacto_out_stream_valid), // .valid
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.out_data (transacto_out_stream_data), // .data
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.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
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.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
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.in_ready (b2p_adapter_out_ready), // in_stream.ready
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.in_valid (b2p_adapter_out_valid), // .valid
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.in_data (b2p_adapter_out_data), // .data
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.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
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.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
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.address (master_address), // avalon_master.address
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.readdata (master_readdata), // .readdata
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.read (master_read), // .read
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.write (master_write), // .write
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.writedata (master_writedata), // .writedata
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.waitrequest (master_waitrequest), // .waitrequest
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.readdatavalid (master_readdatavalid), // .readdatavalid
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.byteenable (master_byteenable) // .byteenable
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);
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ddr3_dmaster_b2p_adapter b2p_adapter (
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.clk (clk_clk), // clk.clk
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.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
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.in_data (b2p_out_packets_stream_data), // in.data
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.in_valid (b2p_out_packets_stream_valid), // .valid
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.in_ready (b2p_out_packets_stream_ready), // .ready
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.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
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.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
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.in_channel (b2p_out_packets_stream_channel), // .channel
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.out_data (b2p_adapter_out_data), // out.data
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.out_valid (b2p_adapter_out_valid), // .valid
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.out_ready (b2p_adapter_out_ready), // .ready
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.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
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.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
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|
);
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||
|
|
|
||
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ddr3_dmaster_p2b_adapter p2b_adapter (
|
||
|
|
.clk (clk_clk), // clk.clk
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||
|
|
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
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||
|
|
.in_data (transacto_out_stream_data), // in.data
|
||
|
|
.in_valid (transacto_out_stream_valid), // .valid
|
||
|
|
.in_ready (transacto_out_stream_ready), // .ready
|
||
|
|
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
|
||
|
|
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
|
||
|
|
.out_data (p2b_adapter_out_data), // out.data
|
||
|
|
.out_valid (p2b_adapter_out_valid), // .valid
|
||
|
|
.out_ready (p2b_adapter_out_ready), // .ready
|
||
|
|
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
|
||
|
|
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
|
||
|
|
.out_channel (p2b_adapter_out_channel) // .channel
|
||
|
|
);
|
||
|
|
|
||
|
|
altera_reset_controller #(
|
||
|
|
.NUM_RESET_INPUTS (1),
|
||
|
|
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
|
||
|
|
.SYNC_DEPTH (2),
|
||
|
|
.RESET_REQUEST_PRESENT (0),
|
||
|
|
.RESET_REQ_WAIT_TIME (1),
|
||
|
|
.MIN_RST_ASSERTION_TIME (3),
|
||
|
|
.RESET_REQ_EARLY_DSRT_TIME (1),
|
||
|
|
.USE_RESET_REQUEST_IN0 (0),
|
||
|
|
.USE_RESET_REQUEST_IN1 (0),
|
||
|
|
.USE_RESET_REQUEST_IN2 (0),
|
||
|
|
.USE_RESET_REQUEST_IN3 (0),
|
||
|
|
.USE_RESET_REQUEST_IN4 (0),
|
||
|
|
.USE_RESET_REQUEST_IN5 (0),
|
||
|
|
.USE_RESET_REQUEST_IN6 (0),
|
||
|
|
.USE_RESET_REQUEST_IN7 (0),
|
||
|
|
.USE_RESET_REQUEST_IN8 (0),
|
||
|
|
.USE_RESET_REQUEST_IN9 (0),
|
||
|
|
.USE_RESET_REQUEST_IN10 (0),
|
||
|
|
.USE_RESET_REQUEST_IN11 (0),
|
||
|
|
.USE_RESET_REQUEST_IN12 (0),
|
||
|
|
.USE_RESET_REQUEST_IN13 (0),
|
||
|
|
.USE_RESET_REQUEST_IN14 (0),
|
||
|
|
.USE_RESET_REQUEST_IN15 (0),
|
||
|
|
.ADAPT_RESET_REQUEST (0)
|
||
|
|
) rst_controller (
|
||
|
|
.reset_in0 (clk_reset_reset), // reset_in0.reset
|
||
|
|
.clk (clk_clk), // clk.clk
|
||
|
|
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
|
||
|
|
.reset_req (), // (terminated)
|
||
|
|
.reset_req_in0 (1'b0), // (terminated)
|
||
|
|
.reset_in1 (1'b0), // (terminated)
|
||
|
|
.reset_req_in1 (1'b0), // (terminated)
|
||
|
|
.reset_in2 (1'b0), // (terminated)
|
||
|
|
.reset_req_in2 (1'b0), // (terminated)
|
||
|
|
.reset_in3 (1'b0), // (terminated)
|
||
|
|
.reset_req_in3 (1'b0), // (terminated)
|
||
|
|
.reset_in4 (1'b0), // (terminated)
|
||
|
|
.reset_req_in4 (1'b0), // (terminated)
|
||
|
|
.reset_in5 (1'b0), // (terminated)
|
||
|
|
.reset_req_in5 (1'b0), // (terminated)
|
||
|
|
.reset_in6 (1'b0), // (terminated)
|
||
|
|
.reset_req_in6 (1'b0), // (terminated)
|
||
|
|
.reset_in7 (1'b0), // (terminated)
|
||
|
|
.reset_req_in7 (1'b0), // (terminated)
|
||
|
|
.reset_in8 (1'b0), // (terminated)
|
||
|
|
.reset_req_in8 (1'b0), // (terminated)
|
||
|
|
.reset_in9 (1'b0), // (terminated)
|
||
|
|
.reset_req_in9 (1'b0), // (terminated)
|
||
|
|
.reset_in10 (1'b0), // (terminated)
|
||
|
|
.reset_req_in10 (1'b0), // (terminated)
|
||
|
|
.reset_in11 (1'b0), // (terminated)
|
||
|
|
.reset_req_in11 (1'b0), // (terminated)
|
||
|
|
.reset_in12 (1'b0), // (terminated)
|
||
|
|
.reset_req_in12 (1'b0), // (terminated)
|
||
|
|
.reset_in13 (1'b0), // (terminated)
|
||
|
|
.reset_req_in13 (1'b0), // (terminated)
|
||
|
|
.reset_in14 (1'b0), // (terminated)
|
||
|
|
.reset_req_in14 (1'b0), // (terminated)
|
||
|
|
.reset_in15 (1'b0), // (terminated)
|
||
|
|
.reset_req_in15 (1'b0) // (terminated)
|
||
|
|
);
|
||
|
|
|
||
|
|
endmodule
|