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mor1kx-bemicrocv/ip/altera/ddr3/ddr3_s0_mm_interconnect_0.v

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2016-08-04 19:22:38 +02:00
// ddr3_s0_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module ddr3_s0_mm_interconnect_0 (
input wire avl_clk_out_clk_clk, // avl_clk_out_clk.clk
input wire cpu_inst_reset_n_reset_bridge_in_reset_reset, // cpu_inst_reset_n_reset_bridge_in_reset.reset
input wire [19:0] cpu_inst_data_master_address, // cpu_inst_data_master.address
output wire cpu_inst_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_inst_data_master_byteenable, // .byteenable
input wire cpu_inst_data_master_read, // .read
output wire [31:0] cpu_inst_data_master_readdata, // .readdata
input wire cpu_inst_data_master_write, // .write
input wire [31:0] cpu_inst_data_master_writedata, // .writedata
input wire [16:0] cpu_inst_instruction_master_address, // cpu_inst_instruction_master.address
output wire cpu_inst_instruction_master_waitrequest, // .waitrequest
input wire cpu_inst_instruction_master_read, // .read
output wire [31:0] cpu_inst_instruction_master_readdata, // .readdata
input wire [31:0] seq_bridge_m0_address, // seq_bridge_m0.address
output wire seq_bridge_m0_waitrequest, // .waitrequest
input wire [0:0] seq_bridge_m0_burstcount, // .burstcount
input wire [3:0] seq_bridge_m0_byteenable, // .byteenable
input wire seq_bridge_m0_read, // .read
output wire [31:0] seq_bridge_m0_readdata, // .readdata
output wire seq_bridge_m0_readdatavalid, // .readdatavalid
input wire seq_bridge_m0_write, // .write
input wire [31:0] seq_bridge_m0_writedata, // .writedata
input wire seq_bridge_m0_debugaccess, // .debugaccess
output wire [15:0] hphy_bridge_s0_address, // hphy_bridge_s0.address
output wire hphy_bridge_s0_write, // .write
output wire hphy_bridge_s0_read, // .read
input wire [31:0] hphy_bridge_s0_readdata, // .readdata
output wire [31:0] hphy_bridge_s0_writedata, // .writedata
input wire hphy_bridge_s0_waitrequest, // .waitrequest
output wire [12:0] sequencer_mem_s1_address, // sequencer_mem_s1.address
output wire sequencer_mem_s1_write, // .write
input wire [31:0] sequencer_mem_s1_readdata, // .readdata
output wire [31:0] sequencer_mem_s1_writedata, // .writedata
output wire [3:0] sequencer_mem_s1_byteenable, // .byteenable
output wire sequencer_mem_s1_chipselect, // .chipselect
output wire [3:0] sequencer_reg_file_inst_avl_address, // sequencer_reg_file_inst_avl.address
output wire sequencer_reg_file_inst_avl_write, // .write
output wire sequencer_reg_file_inst_avl_read, // .read
input wire [31:0] sequencer_reg_file_inst_avl_readdata, // .readdata
output wire [31:0] sequencer_reg_file_inst_avl_writedata, // .writedata
output wire [3:0] sequencer_reg_file_inst_avl_byteenable, // .byteenable
input wire sequencer_reg_file_inst_avl_waitrequest, // .waitrequest
output wire [12:0] sequencer_scc_mgr_inst_avl_address, // sequencer_scc_mgr_inst_avl.address
output wire sequencer_scc_mgr_inst_avl_write, // .write
output wire sequencer_scc_mgr_inst_avl_read, // .read
input wire [31:0] sequencer_scc_mgr_inst_avl_readdata, // .readdata
output wire [31:0] sequencer_scc_mgr_inst_avl_writedata, // .writedata
input wire sequencer_scc_mgr_inst_avl_waitrequest // .waitrequest
);
wire cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_data_master_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata; // cpu_inst_data_master_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
wire cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_agent:av_debugaccess
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_address; // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_agent:av_address
wire cpu_inst_data_master_translator_avalon_universal_master_0_read; // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_agent:av_read
wire [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_agent:av_byteenable
wire cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
wire cpu_inst_data_master_translator_avalon_universal_master_0_lock; // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_agent:av_lock
wire cpu_inst_data_master_translator_avalon_universal_master_0_write; // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_agent:av_write
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata; // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_agent:av_writedata
wire [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_inst_data_master_agent:rp_valid
wire [105:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_inst_data_master_agent:rp_data
wire rsp_mux_src_ready; // cpu_inst_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [3:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_inst_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_inst_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_inst_data_master_agent:rp_endofpacket
wire seq_bridge_m0_translator_avalon_universal_master_0_waitrequest; // seq_bridge_m0_agent:av_waitrequest -> seq_bridge_m0_translator:uav_waitrequest
wire [31:0] seq_bridge_m0_translator_avalon_universal_master_0_readdata; // seq_bridge_m0_agent:av_readdata -> seq_bridge_m0_translator:uav_readdata
wire seq_bridge_m0_translator_avalon_universal_master_0_debugaccess; // seq_bridge_m0_translator:uav_debugaccess -> seq_bridge_m0_agent:av_debugaccess
wire [31:0] seq_bridge_m0_translator_avalon_universal_master_0_address; // seq_bridge_m0_translator:uav_address -> seq_bridge_m0_agent:av_address
wire seq_bridge_m0_translator_avalon_universal_master_0_read; // seq_bridge_m0_translator:uav_read -> seq_bridge_m0_agent:av_read
wire [3:0] seq_bridge_m0_translator_avalon_universal_master_0_byteenable; // seq_bridge_m0_translator:uav_byteenable -> seq_bridge_m0_agent:av_byteenable
wire seq_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // seq_bridge_m0_agent:av_readdatavalid -> seq_bridge_m0_translator:uav_readdatavalid
wire seq_bridge_m0_translator_avalon_universal_master_0_lock; // seq_bridge_m0_translator:uav_lock -> seq_bridge_m0_agent:av_lock
wire seq_bridge_m0_translator_avalon_universal_master_0_write; // seq_bridge_m0_translator:uav_write -> seq_bridge_m0_agent:av_write
wire [31:0] seq_bridge_m0_translator_avalon_universal_master_0_writedata; // seq_bridge_m0_translator:uav_writedata -> seq_bridge_m0_agent:av_writedata
wire [2:0] seq_bridge_m0_translator_avalon_universal_master_0_burstcount; // seq_bridge_m0_translator:uav_burstcount -> seq_bridge_m0_agent:av_burstcount
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_instruction_master_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_inst_instruction_master_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_agent:av_debugaccess
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address; // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_agent:av_address
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_read; // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_agent:av_read
wire [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_agent:av_byteenable
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_instruction_master_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_lock; // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_agent:av_lock
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_write; // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_agent:av_write
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_agent:av_writedata
wire [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_agent:av_burstcount
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> cpu_inst_instruction_master_agent:rp_valid
wire [105:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> cpu_inst_instruction_master_agent:rp_data
wire rsp_mux_002_src_ready; // cpu_inst_instruction_master_agent:rp_ready -> rsp_mux_002:src_ready
wire [3:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> cpu_inst_instruction_master_agent:rp_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> cpu_inst_instruction_master_agent:rp_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> cpu_inst_instruction_master_agent:rp_endofpacket
wire [31:0] hphy_bridge_s0_agent_m0_readdata; // hphy_bridge_s0_translator:uav_readdata -> hphy_bridge_s0_agent:m0_readdata
wire hphy_bridge_s0_agent_m0_waitrequest; // hphy_bridge_s0_translator:uav_waitrequest -> hphy_bridge_s0_agent:m0_waitrequest
wire hphy_bridge_s0_agent_m0_debugaccess; // hphy_bridge_s0_agent:m0_debugaccess -> hphy_bridge_s0_translator:uav_debugaccess
wire [31:0] hphy_bridge_s0_agent_m0_address; // hphy_bridge_s0_agent:m0_address -> hphy_bridge_s0_translator:uav_address
wire [3:0] hphy_bridge_s0_agent_m0_byteenable; // hphy_bridge_s0_agent:m0_byteenable -> hphy_bridge_s0_translator:uav_byteenable
wire hphy_bridge_s0_agent_m0_read; // hphy_bridge_s0_agent:m0_read -> hphy_bridge_s0_translator:uav_read
wire hphy_bridge_s0_agent_m0_readdatavalid; // hphy_bridge_s0_translator:uav_readdatavalid -> hphy_bridge_s0_agent:m0_readdatavalid
wire hphy_bridge_s0_agent_m0_lock; // hphy_bridge_s0_agent:m0_lock -> hphy_bridge_s0_translator:uav_lock
wire [31:0] hphy_bridge_s0_agent_m0_writedata; // hphy_bridge_s0_agent:m0_writedata -> hphy_bridge_s0_translator:uav_writedata
wire hphy_bridge_s0_agent_m0_write; // hphy_bridge_s0_agent:m0_write -> hphy_bridge_s0_translator:uav_write
wire [2:0] hphy_bridge_s0_agent_m0_burstcount; // hphy_bridge_s0_agent:m0_burstcount -> hphy_bridge_s0_translator:uav_burstcount
wire hphy_bridge_s0_agent_rf_source_valid; // hphy_bridge_s0_agent:rf_source_valid -> hphy_bridge_s0_agent_rsp_fifo:in_valid
wire [106:0] hphy_bridge_s0_agent_rf_source_data; // hphy_bridge_s0_agent:rf_source_data -> hphy_bridge_s0_agent_rsp_fifo:in_data
wire hphy_bridge_s0_agent_rf_source_ready; // hphy_bridge_s0_agent_rsp_fifo:in_ready -> hphy_bridge_s0_agent:rf_source_ready
wire hphy_bridge_s0_agent_rf_source_startofpacket; // hphy_bridge_s0_agent:rf_source_startofpacket -> hphy_bridge_s0_agent_rsp_fifo:in_startofpacket
wire hphy_bridge_s0_agent_rf_source_endofpacket; // hphy_bridge_s0_agent:rf_source_endofpacket -> hphy_bridge_s0_agent_rsp_fifo:in_endofpacket
wire hphy_bridge_s0_agent_rsp_fifo_out_valid; // hphy_bridge_s0_agent_rsp_fifo:out_valid -> hphy_bridge_s0_agent:rf_sink_valid
wire [106:0] hphy_bridge_s0_agent_rsp_fifo_out_data; // hphy_bridge_s0_agent_rsp_fifo:out_data -> hphy_bridge_s0_agent:rf_sink_data
wire hphy_bridge_s0_agent_rsp_fifo_out_ready; // hphy_bridge_s0_agent:rf_sink_ready -> hphy_bridge_s0_agent_rsp_fifo:out_ready
wire hphy_bridge_s0_agent_rsp_fifo_out_startofpacket; // hphy_bridge_s0_agent_rsp_fifo:out_startofpacket -> hphy_bridge_s0_agent:rf_sink_startofpacket
wire hphy_bridge_s0_agent_rsp_fifo_out_endofpacket; // hphy_bridge_s0_agent_rsp_fifo:out_endofpacket -> hphy_bridge_s0_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> hphy_bridge_s0_agent:cp_valid
wire [105:0] cmd_mux_src_data; // cmd_mux:src_data -> hphy_bridge_s0_agent:cp_data
wire cmd_mux_src_ready; // hphy_bridge_s0_agent:cp_ready -> cmd_mux:src_ready
wire [3:0] cmd_mux_src_channel; // cmd_mux:src_channel -> hphy_bridge_s0_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> hphy_bridge_s0_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> hphy_bridge_s0_agent:cp_endofpacket
wire [31:0] sequencer_mem_s1_agent_m0_readdata; // sequencer_mem_s1_translator:uav_readdata -> sequencer_mem_s1_agent:m0_readdata
wire sequencer_mem_s1_agent_m0_waitrequest; // sequencer_mem_s1_translator:uav_waitrequest -> sequencer_mem_s1_agent:m0_waitrequest
wire sequencer_mem_s1_agent_m0_debugaccess; // sequencer_mem_s1_agent:m0_debugaccess -> sequencer_mem_s1_translator:uav_debugaccess
wire [31:0] sequencer_mem_s1_agent_m0_address; // sequencer_mem_s1_agent:m0_address -> sequencer_mem_s1_translator:uav_address
wire [3:0] sequencer_mem_s1_agent_m0_byteenable; // sequencer_mem_s1_agent:m0_byteenable -> sequencer_mem_s1_translator:uav_byteenable
wire sequencer_mem_s1_agent_m0_read; // sequencer_mem_s1_agent:m0_read -> sequencer_mem_s1_translator:uav_read
wire sequencer_mem_s1_agent_m0_readdatavalid; // sequencer_mem_s1_translator:uav_readdatavalid -> sequencer_mem_s1_agent:m0_readdatavalid
wire sequencer_mem_s1_agent_m0_lock; // sequencer_mem_s1_agent:m0_lock -> sequencer_mem_s1_translator:uav_lock
wire [31:0] sequencer_mem_s1_agent_m0_writedata; // sequencer_mem_s1_agent:m0_writedata -> sequencer_mem_s1_translator:uav_writedata
wire sequencer_mem_s1_agent_m0_write; // sequencer_mem_s1_agent:m0_write -> sequencer_mem_s1_translator:uav_write
wire [2:0] sequencer_mem_s1_agent_m0_burstcount; // sequencer_mem_s1_agent:m0_burstcount -> sequencer_mem_s1_translator:uav_burstcount
wire sequencer_mem_s1_agent_rf_source_valid; // sequencer_mem_s1_agent:rf_source_valid -> sequencer_mem_s1_agent_rsp_fifo:in_valid
wire [106:0] sequencer_mem_s1_agent_rf_source_data; // sequencer_mem_s1_agent:rf_source_data -> sequencer_mem_s1_agent_rsp_fifo:in_data
wire sequencer_mem_s1_agent_rf_source_ready; // sequencer_mem_s1_agent_rsp_fifo:in_ready -> sequencer_mem_s1_agent:rf_source_ready
wire sequencer_mem_s1_agent_rf_source_startofpacket; // sequencer_mem_s1_agent:rf_source_startofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_startofpacket
wire sequencer_mem_s1_agent_rf_source_endofpacket; // sequencer_mem_s1_agent:rf_source_endofpacket -> sequencer_mem_s1_agent_rsp_fifo:in_endofpacket
wire sequencer_mem_s1_agent_rsp_fifo_out_valid; // sequencer_mem_s1_agent_rsp_fifo:out_valid -> sequencer_mem_s1_agent:rf_sink_valid
wire [106:0] sequencer_mem_s1_agent_rsp_fifo_out_data; // sequencer_mem_s1_agent_rsp_fifo:out_data -> sequencer_mem_s1_agent:rf_sink_data
wire sequencer_mem_s1_agent_rsp_fifo_out_ready; // sequencer_mem_s1_agent:rf_sink_ready -> sequencer_mem_s1_agent_rsp_fifo:out_ready
wire sequencer_mem_s1_agent_rsp_fifo_out_startofpacket; // sequencer_mem_s1_agent_rsp_fifo:out_startofpacket -> sequencer_mem_s1_agent:rf_sink_startofpacket
wire sequencer_mem_s1_agent_rsp_fifo_out_endofpacket; // sequencer_mem_s1_agent_rsp_fifo:out_endofpacket -> sequencer_mem_s1_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> sequencer_mem_s1_agent:cp_valid
wire [105:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> sequencer_mem_s1_agent:cp_data
wire cmd_mux_001_src_ready; // sequencer_mem_s1_agent:cp_ready -> cmd_mux_001:src_ready
wire [3:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> sequencer_mem_s1_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> sequencer_mem_s1_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> sequencer_mem_s1_agent:cp_endofpacket
wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_readdata; // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_agent:m0_readdata
wire sequencer_scc_mgr_inst_avl_agent_m0_waitrequest; // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_agent:m0_waitrequest
wire sequencer_scc_mgr_inst_avl_agent_m0_debugaccess; // sequencer_scc_mgr_inst_avl_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess
wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_address; // sequencer_scc_mgr_inst_avl_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address
wire [3:0] sequencer_scc_mgr_inst_avl_agent_m0_byteenable; // sequencer_scc_mgr_inst_avl_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable
wire sequencer_scc_mgr_inst_avl_agent_m0_read; // sequencer_scc_mgr_inst_avl_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read
wire sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid; // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_agent:m0_readdatavalid
wire sequencer_scc_mgr_inst_avl_agent_m0_lock; // sequencer_scc_mgr_inst_avl_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock
wire [31:0] sequencer_scc_mgr_inst_avl_agent_m0_writedata; // sequencer_scc_mgr_inst_avl_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata
wire sequencer_scc_mgr_inst_avl_agent_m0_write; // sequencer_scc_mgr_inst_avl_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write
wire [2:0] sequencer_scc_mgr_inst_avl_agent_m0_burstcount; // sequencer_scc_mgr_inst_avl_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount
wire sequencer_scc_mgr_inst_avl_agent_rf_source_valid; // sequencer_scc_mgr_inst_avl_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_valid
wire [106:0] sequencer_scc_mgr_inst_avl_agent_rf_source_data; // sequencer_scc_mgr_inst_avl_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_data
wire sequencer_scc_mgr_inst_avl_agent_rf_source_ready; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_agent:rf_source_ready
wire sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket; // sequencer_scc_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
wire sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket; // sequencer_scc_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_agent:rf_sink_valid
wire [106:0] sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_agent:rf_sink_data
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready; // sequencer_scc_mgr_inst_avl_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_ready
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_agent:rf_sink_startofpacket
wire sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_scc_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sequencer_scc_mgr_inst_avl_agent:cp_valid
wire [105:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sequencer_scc_mgr_inst_avl_agent:cp_data
wire cmd_mux_002_src_ready; // sequencer_scc_mgr_inst_avl_agent:cp_ready -> cmd_mux_002:src_ready
wire [3:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sequencer_scc_mgr_inst_avl_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sequencer_scc_mgr_inst_avl_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sequencer_scc_mgr_inst_avl_agent:cp_endofpacket
wire [31:0] sequencer_reg_file_inst_avl_agent_m0_readdata; // sequencer_reg_file_inst_avl_translator:uav_readdata -> sequencer_reg_file_inst_avl_agent:m0_readdata
wire sequencer_reg_file_inst_avl_agent_m0_waitrequest; // sequencer_reg_file_inst_avl_translator:uav_waitrequest -> sequencer_reg_file_inst_avl_agent:m0_waitrequest
wire sequencer_reg_file_inst_avl_agent_m0_debugaccess; // sequencer_reg_file_inst_avl_agent:m0_debugaccess -> sequencer_reg_file_inst_avl_translator:uav_debugaccess
wire [31:0] sequencer_reg_file_inst_avl_agent_m0_address; // sequencer_reg_file_inst_avl_agent:m0_address -> sequencer_reg_file_inst_avl_translator:uav_address
wire [3:0] sequencer_reg_file_inst_avl_agent_m0_byteenable; // sequencer_reg_file_inst_avl_agent:m0_byteenable -> sequencer_reg_file_inst_avl_translator:uav_byteenable
wire sequencer_reg_file_inst_avl_agent_m0_read; // sequencer_reg_file_inst_avl_agent:m0_read -> sequencer_reg_file_inst_avl_translator:uav_read
wire sequencer_reg_file_inst_avl_agent_m0_readdatavalid; // sequencer_reg_file_inst_avl_translator:uav_readdatavalid -> sequencer_reg_file_inst_avl_agent:m0_readdatavalid
wire sequencer_reg_file_inst_avl_agent_m0_lock; // sequencer_reg_file_inst_avl_agent:m0_lock -> sequencer_reg_file_inst_avl_translator:uav_lock
wire [31:0] sequencer_reg_file_inst_avl_agent_m0_writedata; // sequencer_reg_file_inst_avl_agent:m0_writedata -> sequencer_reg_file_inst_avl_translator:uav_writedata
wire sequencer_reg_file_inst_avl_agent_m0_write; // sequencer_reg_file_inst_avl_agent:m0_write -> sequencer_reg_file_inst_avl_translator:uav_write
wire [2:0] sequencer_reg_file_inst_avl_agent_m0_burstcount; // sequencer_reg_file_inst_avl_agent:m0_burstcount -> sequencer_reg_file_inst_avl_translator:uav_burstcount
wire sequencer_reg_file_inst_avl_agent_rf_source_valid; // sequencer_reg_file_inst_avl_agent:rf_source_valid -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_valid
wire [106:0] sequencer_reg_file_inst_avl_agent_rf_source_data; // sequencer_reg_file_inst_avl_agent:rf_source_data -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_data
wire sequencer_reg_file_inst_avl_agent_rf_source_ready; // sequencer_reg_file_inst_avl_agent_rsp_fifo:in_ready -> sequencer_reg_file_inst_avl_agent:rf_source_ready
wire sequencer_reg_file_inst_avl_agent_rf_source_startofpacket; // sequencer_reg_file_inst_avl_agent:rf_source_startofpacket -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_startofpacket
wire sequencer_reg_file_inst_avl_agent_rf_source_endofpacket; // sequencer_reg_file_inst_avl_agent:rf_source_endofpacket -> sequencer_reg_file_inst_avl_agent_rsp_fifo:in_endofpacket
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_valid -> sequencer_reg_file_inst_avl_agent:rf_sink_valid
wire [106:0] sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_data -> sequencer_reg_file_inst_avl_agent:rf_sink_data
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready; // sequencer_reg_file_inst_avl_agent:rf_sink_ready -> sequencer_reg_file_inst_avl_agent_rsp_fifo:out_ready
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_reg_file_inst_avl_agent:rf_sink_startofpacket
wire sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket; // sequencer_reg_file_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_reg_file_inst_avl_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sequencer_reg_file_inst_avl_agent:cp_valid
wire [105:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sequencer_reg_file_inst_avl_agent:cp_data
wire cmd_mux_003_src_ready; // sequencer_reg_file_inst_avl_agent:cp_ready -> cmd_mux_003:src_ready
wire [3:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sequencer_reg_file_inst_avl_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sequencer_reg_file_inst_avl_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sequencer_reg_file_inst_avl_agent:cp_endofpacket
wire cpu_inst_data_master_agent_cp_valid; // cpu_inst_data_master_agent:cp_valid -> router:sink_valid
wire [105:0] cpu_inst_data_master_agent_cp_data; // cpu_inst_data_master_agent:cp_data -> router:sink_data
wire cpu_inst_data_master_agent_cp_ready; // router:sink_ready -> cpu_inst_data_master_agent:cp_ready
wire cpu_inst_data_master_agent_cp_startofpacket; // cpu_inst_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire cpu_inst_data_master_agent_cp_endofpacket; // cpu_inst_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [105:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [3:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire seq_bridge_m0_agent_cp_valid; // seq_bridge_m0_agent:cp_valid -> router_001:sink_valid
wire [105:0] seq_bridge_m0_agent_cp_data; // seq_bridge_m0_agent:cp_data -> router_001:sink_data
wire seq_bridge_m0_agent_cp_ready; // router_001:sink_ready -> seq_bridge_m0_agent:cp_ready
wire seq_bridge_m0_agent_cp_startofpacket; // seq_bridge_m0_agent:cp_startofpacket -> router_001:sink_startofpacket
wire seq_bridge_m0_agent_cp_endofpacket; // seq_bridge_m0_agent:cp_endofpacket -> router_001:sink_endofpacket
wire cpu_inst_instruction_master_agent_cp_valid; // cpu_inst_instruction_master_agent:cp_valid -> router_002:sink_valid
wire [105:0] cpu_inst_instruction_master_agent_cp_data; // cpu_inst_instruction_master_agent:cp_data -> router_002:sink_data
wire cpu_inst_instruction_master_agent_cp_ready; // router_002:sink_ready -> cpu_inst_instruction_master_agent:cp_ready
wire cpu_inst_instruction_master_agent_cp_startofpacket; // cpu_inst_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire cpu_inst_instruction_master_agent_cp_endofpacket; // cpu_inst_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> cmd_demux_002:sink_valid
wire [105:0] router_002_src_data; // router_002:src_data -> cmd_demux_002:sink_data
wire router_002_src_ready; // cmd_demux_002:sink_ready -> router_002:src_ready
wire [3:0] router_002_src_channel; // router_002:src_channel -> cmd_demux_002:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
wire hphy_bridge_s0_agent_rp_valid; // hphy_bridge_s0_agent:rp_valid -> router_003:sink_valid
wire [105:0] hphy_bridge_s0_agent_rp_data; // hphy_bridge_s0_agent:rp_data -> router_003:sink_data
wire hphy_bridge_s0_agent_rp_ready; // router_003:sink_ready -> hphy_bridge_s0_agent:rp_ready
wire hphy_bridge_s0_agent_rp_startofpacket; // hphy_bridge_s0_agent:rp_startofpacket -> router_003:sink_startofpacket
wire hphy_bridge_s0_agent_rp_endofpacket; // hphy_bridge_s0_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux:sink_valid
wire [105:0] router_003_src_data; // router_003:src_data -> rsp_demux:sink_data
wire router_003_src_ready; // rsp_demux:sink_ready -> router_003:src_ready
wire [3:0] router_003_src_channel; // router_003:src_channel -> rsp_demux:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux:sink_endofpacket
wire sequencer_mem_s1_agent_rp_valid; // sequencer_mem_s1_agent:rp_valid -> router_004:sink_valid
wire [105:0] sequencer_mem_s1_agent_rp_data; // sequencer_mem_s1_agent:rp_data -> router_004:sink_data
wire sequencer_mem_s1_agent_rp_ready; // router_004:sink_ready -> sequencer_mem_s1_agent:rp_ready
wire sequencer_mem_s1_agent_rp_startofpacket; // sequencer_mem_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
wire sequencer_mem_s1_agent_rp_endofpacket; // sequencer_mem_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid
wire [105:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data
wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready
wire [3:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire sequencer_scc_mgr_inst_avl_agent_rp_valid; // sequencer_scc_mgr_inst_avl_agent:rp_valid -> router_005:sink_valid
wire [105:0] sequencer_scc_mgr_inst_avl_agent_rp_data; // sequencer_scc_mgr_inst_avl_agent:rp_data -> router_005:sink_data
wire sequencer_scc_mgr_inst_avl_agent_rp_ready; // router_005:sink_ready -> sequencer_scc_mgr_inst_avl_agent:rp_ready
wire sequencer_scc_mgr_inst_avl_agent_rp_startofpacket; // sequencer_scc_mgr_inst_avl_agent:rp_startofpacket -> router_005:sink_startofpacket
wire sequencer_scc_mgr_inst_avl_agent_rp_endofpacket; // sequencer_scc_mgr_inst_avl_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_002:sink_valid
wire [105:0] router_005_src_data; // router_005:src_data -> rsp_demux_002:sink_data
wire router_005_src_ready; // rsp_demux_002:sink_ready -> router_005:src_ready
wire [3:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_002:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire sequencer_reg_file_inst_avl_agent_rp_valid; // sequencer_reg_file_inst_avl_agent:rp_valid -> router_006:sink_valid
wire [105:0] sequencer_reg_file_inst_avl_agent_rp_data; // sequencer_reg_file_inst_avl_agent:rp_data -> router_006:sink_data
wire sequencer_reg_file_inst_avl_agent_rp_ready; // router_006:sink_ready -> sequencer_reg_file_inst_avl_agent:rp_ready
wire sequencer_reg_file_inst_avl_agent_rp_startofpacket; // sequencer_reg_file_inst_avl_agent:rp_startofpacket -> router_006:sink_startofpacket
wire sequencer_reg_file_inst_avl_agent_rp_endofpacket; // sequencer_reg_file_inst_avl_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid
wire [105:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data
wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready
wire [3:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> seq_bridge_m0_limiter:cmd_sink_valid
wire [105:0] router_001_src_data; // router_001:src_data -> seq_bridge_m0_limiter:cmd_sink_data
wire router_001_src_ready; // seq_bridge_m0_limiter:cmd_sink_ready -> router_001:src_ready
wire [3:0] router_001_src_channel; // router_001:src_channel -> seq_bridge_m0_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> seq_bridge_m0_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> seq_bridge_m0_limiter:cmd_sink_endofpacket
wire [105:0] seq_bridge_m0_limiter_cmd_src_data; // seq_bridge_m0_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire seq_bridge_m0_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> seq_bridge_m0_limiter:cmd_src_ready
wire [3:0] seq_bridge_m0_limiter_cmd_src_channel; // seq_bridge_m0_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire seq_bridge_m0_limiter_cmd_src_startofpacket; // seq_bridge_m0_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire seq_bridge_m0_limiter_cmd_src_endofpacket; // seq_bridge_m0_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> seq_bridge_m0_limiter:rsp_sink_valid
wire [105:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> seq_bridge_m0_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // seq_bridge_m0_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [3:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> seq_bridge_m0_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> seq_bridge_m0_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> seq_bridge_m0_limiter:rsp_sink_endofpacket
wire seq_bridge_m0_limiter_rsp_src_valid; // seq_bridge_m0_limiter:rsp_src_valid -> seq_bridge_m0_agent:rp_valid
wire [105:0] seq_bridge_m0_limiter_rsp_src_data; // seq_bridge_m0_limiter:rsp_src_data -> seq_bridge_m0_agent:rp_data
wire seq_bridge_m0_limiter_rsp_src_ready; // seq_bridge_m0_agent:rp_ready -> seq_bridge_m0_limiter:rsp_src_ready
wire [3:0] seq_bridge_m0_limiter_rsp_src_channel; // seq_bridge_m0_limiter:rsp_src_channel -> seq_bridge_m0_agent:rp_channel
wire seq_bridge_m0_limiter_rsp_src_startofpacket; // seq_bridge_m0_limiter:rsp_src_startofpacket -> seq_bridge_m0_agent:rp_startofpacket
wire seq_bridge_m0_limiter_rsp_src_endofpacket; // seq_bridge_m0_limiter:rsp_src_endofpacket -> seq_bridge_m0_agent:rp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [105:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [3:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [105:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [3:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [105:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [3:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [105:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [3:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
wire [105:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
wire [3:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_003:sink1_valid
wire [105:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_003:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src1_ready
wire [3:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_003:sink1_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux_001:sink2_valid
wire [105:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux_001:sink2_data
wire cmd_demux_002_src0_ready; // cmd_mux_001:sink2_ready -> cmd_demux_002:src0_ready
wire [3:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux_001:sink2_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux_001:sink2_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux_001:sink2_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [105:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [3:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [105:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [3:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
wire [105:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
wire [3:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src2_valid; // rsp_demux_001:src2_valid -> rsp_mux_002:sink0_valid
wire [105:0] rsp_demux_001_src2_data; // rsp_demux_001:src2_data -> rsp_mux_002:sink0_data
wire rsp_demux_001_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux_001:src2_ready
wire [3:0] rsp_demux_001_src2_channel; // rsp_demux_001:src2_channel -> rsp_mux_002:sink0_channel
wire rsp_demux_001_src2_startofpacket; // rsp_demux_001:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
wire rsp_demux_001_src2_endofpacket; // rsp_demux_001:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [105:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [3:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [105:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [3:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink1_valid
wire [105:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_003_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_003:src1_ready
wire [3:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire [3:0] seq_bridge_m0_limiter_cmd_valid_data; // seq_bridge_m0_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire hphy_bridge_s0_agent_rdata_fifo_src_valid; // hphy_bridge_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] hphy_bridge_s0_agent_rdata_fifo_src_data; // hphy_bridge_s0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire hphy_bridge_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> hphy_bridge_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> hphy_bridge_s0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> hphy_bridge_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // hphy_bridge_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> hphy_bridge_s0_agent:rdata_fifo_sink_error
wire sequencer_mem_s1_agent_rdata_fifo_src_valid; // sequencer_mem_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] sequencer_mem_s1_agent_rdata_fifo_src_data; // sequencer_mem_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire sequencer_mem_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> sequencer_mem_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> sequencer_mem_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> sequencer_mem_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // sequencer_mem_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> sequencer_mem_s1_agent:rdata_fifo_sink_error
wire sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> sequencer_scc_mgr_inst_avl_agent:rdata_fifo_sink_error
wire sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid; // sequencer_reg_file_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data; // sequencer_reg_file_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> sequencer_reg_file_inst_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sequencer_reg_file_inst_avl_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_inst_data_master_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.av_read (cpu_inst_data_master_read), // .read
.av_readdata (cpu_inst_data_master_readdata), // .readdata
.av_write (cpu_inst_data_master_write), // .write
.av_writedata (cpu_inst_data_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) seq_bridge_m0_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (seq_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (seq_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (seq_bridge_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (seq_bridge_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (seq_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (seq_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (seq_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (seq_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (seq_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (seq_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (seq_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (seq_bridge_m0_address), // avalon_anti_master_0.address
.av_waitrequest (seq_bridge_m0_waitrequest), // .waitrequest
.av_burstcount (seq_bridge_m0_burstcount), // .burstcount
.av_byteenable (seq_bridge_m0_byteenable), // .byteenable
.av_read (seq_bridge_m0_read), // .read
.av_readdata (seq_bridge_m0_readdata), // .readdata
.av_readdatavalid (seq_bridge_m0_readdatavalid), // .readdatavalid
.av_write (seq_bridge_m0_write), // .write
.av_writedata (seq_bridge_m0_writedata), // .writedata
.av_debugaccess (seq_bridge_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (17),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_inst_instruction_master_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_inst_instruction_master_read), // .read
.av_readdata (cpu_inst_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hphy_bridge_s0_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hphy_bridge_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hphy_bridge_s0_agent_m0_burstcount), // .burstcount
.uav_read (hphy_bridge_s0_agent_m0_read), // .read
.uav_write (hphy_bridge_s0_agent_m0_write), // .write
.uav_waitrequest (hphy_bridge_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hphy_bridge_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hphy_bridge_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (hphy_bridge_s0_agent_m0_readdata), // .readdata
.uav_writedata (hphy_bridge_s0_agent_m0_writedata), // .writedata
.uav_lock (hphy_bridge_s0_agent_m0_lock), // .lock
.uav_debugaccess (hphy_bridge_s0_agent_m0_debugaccess), // .debugaccess
.av_address (hphy_bridge_s0_address), // avalon_anti_slave_0.address
.av_write (hphy_bridge_s0_write), // .write
.av_read (hphy_bridge_s0_read), // .read
.av_readdata (hphy_bridge_s0_readdata), // .readdata
.av_writedata (hphy_bridge_s0_writedata), // .writedata
.av_waitrequest (hphy_bridge_s0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_mem_s1_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_mem_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_mem_s1_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_mem_s1_agent_m0_read), // .read
.uav_write (sequencer_mem_s1_agent_m0_write), // .write
.uav_waitrequest (sequencer_mem_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_mem_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_mem_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_mem_s1_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_mem_s1_agent_m0_writedata), // .writedata
.uav_lock (sequencer_mem_s1_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_mem_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_mem_s1_address), // avalon_anti_slave_0.address
.av_write (sequencer_mem_s1_write), // .write
.av_readdata (sequencer_mem_s1_readdata), // .readdata
.av_writedata (sequencer_mem_s1_writedata), // .writedata
.av_byteenable (sequencer_mem_s1_byteenable), // .byteenable
.av_chipselect (sequencer_mem_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_scc_mgr_inst_avl_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_scc_mgr_inst_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_scc_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_scc_mgr_inst_avl_agent_m0_read), // .read
.uav_write (sequencer_scc_mgr_inst_avl_agent_m0_write), // .write
.uav_waitrequest (sequencer_scc_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_scc_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_scc_mgr_inst_avl_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_scc_mgr_inst_avl_agent_m0_writedata), // .writedata
.uav_lock (sequencer_scc_mgr_inst_avl_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_scc_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_scc_mgr_inst_avl_address), // avalon_anti_slave_0.address
.av_write (sequencer_scc_mgr_inst_avl_write), // .write
.av_read (sequencer_scc_mgr_inst_avl_read), // .read
.av_readdata (sequencer_scc_mgr_inst_avl_readdata), // .readdata
.av_writedata (sequencer_scc_mgr_inst_avl_writedata), // .writedata
.av_waitrequest (sequencer_scc_mgr_inst_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_reg_file_inst_avl_translator (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sequencer_reg_file_inst_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_reg_file_inst_avl_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_reg_file_inst_avl_agent_m0_read), // .read
.uav_write (sequencer_reg_file_inst_avl_agent_m0_write), // .write
.uav_waitrequest (sequencer_reg_file_inst_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_reg_file_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_reg_file_inst_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_reg_file_inst_avl_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_reg_file_inst_avl_agent_m0_writedata), // .writedata
.uav_lock (sequencer_reg_file_inst_avl_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_reg_file_inst_avl_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_reg_file_inst_avl_address), // avalon_anti_slave_0.address
.av_write (sequencer_reg_file_inst_avl_write), // .write
.av_read (sequencer_reg_file_inst_avl_read), // .read
.av_readdata (sequencer_reg_file_inst_avl_readdata), // .readdata
.av_writedata (sequencer_reg_file_inst_avl_writedata), // .writedata
.av_byteenable (sequencer_reg_file_inst_avl_byteenable), // .byteenable
.av_waitrequest (sequencer_reg_file_inst_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (105),
.PKT_ORI_BURST_SIZE_L (103),
.PKT_RESPONSE_STATUS_H (102),
.PKT_RESPONSE_STATUS_L (101),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_CACHE_H (100),
.PKT_CACHE_L (97),
.PKT_THREAD_ID_H (93),
.PKT_THREAD_ID_L (93),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (96),
.PKT_PROTECTION_L (94),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (92),
.PKT_DEST_ID_L (91),
.ST_DATA_W (106),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_inst_data_master_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (105),
.PKT_ORI_BURST_SIZE_L (103),
.PKT_RESPONSE_STATUS_H (102),
.PKT_RESPONSE_STATUS_L (101),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_CACHE_H (100),
.PKT_CACHE_L (97),
.PKT_THREAD_ID_H (93),
.PKT_THREAD_ID_L (93),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (96),
.PKT_PROTECTION_L (94),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (92),
.PKT_DEST_ID_L (91),
.ST_DATA_W (106),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) seq_bridge_m0_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (seq_bridge_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (seq_bridge_m0_translator_avalon_universal_master_0_write), // .write
.av_read (seq_bridge_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (seq_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (seq_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (seq_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (seq_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (seq_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (seq_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (seq_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (seq_bridge_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (seq_bridge_m0_agent_cp_valid), // cp.valid
.cp_data (seq_bridge_m0_agent_cp_data), // .data
.cp_startofpacket (seq_bridge_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (seq_bridge_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (seq_bridge_m0_agent_cp_ready), // .ready
.rp_valid (seq_bridge_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (seq_bridge_m0_limiter_rsp_src_data), // .data
.rp_channel (seq_bridge_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (seq_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (seq_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (seq_bridge_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (105),
.PKT_ORI_BURST_SIZE_L (103),
.PKT_RESPONSE_STATUS_H (102),
.PKT_RESPONSE_STATUS_L (101),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_CACHE_H (100),
.PKT_CACHE_L (97),
.PKT_THREAD_ID_H (93),
.PKT_THREAD_ID_L (93),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (96),
.PKT_PROTECTION_L (94),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (92),
.PKT_DEST_ID_L (91),
.ST_DATA_W (106),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_inst_instruction_master_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_002_src_valid), // rp.valid
.rp_data (rsp_mux_002_src_data), // .data
.rp_channel (rsp_mux_002_src_channel), // .channel
.rp_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_002_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (105),
.PKT_ORI_BURST_SIZE_L (103),
.PKT_RESPONSE_STATUS_H (102),
.PKT_RESPONSE_STATUS_L (101),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (96),
.PKT_PROTECTION_L (94),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (92),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (106),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hphy_bridge_s0_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hphy_bridge_s0_agent_m0_address), // m0.address
.m0_burstcount (hphy_bridge_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (hphy_bridge_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hphy_bridge_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (hphy_bridge_s0_agent_m0_lock), // .lock
.m0_readdata (hphy_bridge_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (hphy_bridge_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hphy_bridge_s0_agent_m0_read), // .read
.m0_waitrequest (hphy_bridge_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hphy_bridge_s0_agent_m0_writedata), // .writedata
.m0_write (hphy_bridge_s0_agent_m0_write), // .write
.rp_endofpacket (hphy_bridge_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hphy_bridge_s0_agent_rp_ready), // .ready
.rp_valid (hphy_bridge_s0_agent_rp_valid), // .valid
.rp_data (hphy_bridge_s0_agent_rp_data), // .data
.rp_startofpacket (hphy_bridge_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (hphy_bridge_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hphy_bridge_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hphy_bridge_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hphy_bridge_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hphy_bridge_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hphy_bridge_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hphy_bridge_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hphy_bridge_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hphy_bridge_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hphy_bridge_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (hphy_bridge_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hphy_bridge_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hphy_bridge_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (107),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hphy_bridge_s0_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hphy_bridge_s0_agent_rf_source_data), // in.data
.in_valid (hphy_bridge_s0_agent_rf_source_valid), // .valid
.in_ready (hphy_bridge_s0_agent_rf_source_ready), // .ready
.in_startofpacket (hphy_bridge_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hphy_bridge_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (hphy_bridge_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (hphy_bridge_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (hphy_bridge_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hphy_bridge_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hphy_bridge_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (105),
.PKT_ORI_BURST_SIZE_L (103),
.PKT_RESPONSE_STATUS_H (102),
.PKT_RESPONSE_STATUS_L (101),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (96),
.PKT_PROTECTION_L (94),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (92),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (106),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_mem_s1_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_mem_s1_agent_m0_address), // m0.address
.m0_burstcount (sequencer_mem_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_mem_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_mem_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_mem_s1_agent_m0_lock), // .lock
.m0_readdata (sequencer_mem_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_mem_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_mem_s1_agent_m0_read), // .read
.m0_waitrequest (sequencer_mem_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_mem_s1_agent_m0_writedata), // .writedata
.m0_write (sequencer_mem_s1_agent_m0_write), // .write
.rp_endofpacket (sequencer_mem_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_mem_s1_agent_rp_ready), // .ready
.rp_valid (sequencer_mem_s1_agent_rp_valid), // .valid
.rp_data (sequencer_mem_s1_agent_rp_data), // .data
.rp_startofpacket (sequencer_mem_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (sequencer_mem_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_mem_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_mem_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_mem_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_mem_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_mem_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_mem_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_mem_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_mem_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_mem_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_mem_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (107),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_mem_s1_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_mem_s1_agent_rf_source_data), // in.data
.in_valid (sequencer_mem_s1_agent_rf_source_valid), // .valid
.in_ready (sequencer_mem_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_mem_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_mem_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_mem_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_mem_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_mem_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_mem_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_mem_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (105),
.PKT_ORI_BURST_SIZE_L (103),
.PKT_RESPONSE_STATUS_H (102),
.PKT_RESPONSE_STATUS_L (101),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (96),
.PKT_PROTECTION_L (94),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (92),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (106),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_scc_mgr_inst_avl_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_scc_mgr_inst_avl_agent_m0_address), // m0.address
.m0_burstcount (sequencer_scc_mgr_inst_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_scc_mgr_inst_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_scc_mgr_inst_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_scc_mgr_inst_avl_agent_m0_lock), // .lock
.m0_readdata (sequencer_scc_mgr_inst_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_scc_mgr_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_scc_mgr_inst_avl_agent_m0_read), // .read
.m0_waitrequest (sequencer_scc_mgr_inst_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_scc_mgr_inst_avl_agent_m0_writedata), // .writedata
.m0_write (sequencer_scc_mgr_inst_avl_agent_m0_write), // .write
.rp_endofpacket (sequencer_scc_mgr_inst_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_scc_mgr_inst_avl_agent_rp_ready), // .ready
.rp_valid (sequencer_scc_mgr_inst_avl_agent_rp_valid), // .valid
.rp_data (sequencer_scc_mgr_inst_avl_agent_rp_data), // .data
.rp_startofpacket (sequencer_scc_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_scc_mgr_inst_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_scc_mgr_inst_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_scc_mgr_inst_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (107),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_scc_mgr_inst_avl_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_scc_mgr_inst_avl_agent_rf_source_data), // in.data
.in_valid (sequencer_scc_mgr_inst_avl_agent_rf_source_valid), // .valid
.in_ready (sequencer_scc_mgr_inst_avl_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_scc_mgr_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_scc_mgr_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (105),
.PKT_ORI_BURST_SIZE_L (103),
.PKT_RESPONSE_STATUS_H (102),
.PKT_RESPONSE_STATUS_L (101),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (96),
.PKT_PROTECTION_L (94),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (92),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (106),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sequencer_reg_file_inst_avl_agent (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sequencer_reg_file_inst_avl_agent_m0_address), // m0.address
.m0_burstcount (sequencer_reg_file_inst_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_reg_file_inst_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_reg_file_inst_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_reg_file_inst_avl_agent_m0_lock), // .lock
.m0_readdata (sequencer_reg_file_inst_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_reg_file_inst_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_reg_file_inst_avl_agent_m0_read), // .read
.m0_waitrequest (sequencer_reg_file_inst_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_reg_file_inst_avl_agent_m0_writedata), // .writedata
.m0_write (sequencer_reg_file_inst_avl_agent_m0_write), // .write
.rp_endofpacket (sequencer_reg_file_inst_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_reg_file_inst_avl_agent_rp_ready), // .ready
.rp_valid (sequencer_reg_file_inst_avl_agent_rp_valid), // .valid
.rp_data (sequencer_reg_file_inst_avl_agent_rp_data), // .data
.rp_startofpacket (sequencer_reg_file_inst_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_reg_file_inst_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_reg_file_inst_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_reg_file_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_reg_file_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_reg_file_inst_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (107),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_reg_file_inst_avl_agent_rsp_fifo (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sequencer_reg_file_inst_avl_agent_rf_source_data), // in.data
.in_valid (sequencer_reg_file_inst_avl_agent_rf_source_valid), // .valid
.in_ready (sequencer_reg_file_inst_avl_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_reg_file_inst_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_reg_file_inst_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_reg_file_inst_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
ddr3_s0_mm_interconnect_0_router router (
.sink_ready (cpu_inst_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_data_master_agent_cp_valid), // .valid
.sink_data (cpu_inst_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_data_master_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_router_001 router_001 (
.sink_ready (seq_bridge_m0_agent_cp_ready), // sink.ready
.sink_valid (seq_bridge_m0_agent_cp_valid), // .valid
.sink_data (seq_bridge_m0_agent_cp_data), // .data
.sink_startofpacket (seq_bridge_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (seq_bridge_m0_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_router_002 router_002 (
.sink_ready (cpu_inst_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_inst_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_router_003 router_003 (
.sink_ready (hphy_bridge_s0_agent_rp_ready), // sink.ready
.sink_valid (hphy_bridge_s0_agent_rp_valid), // .valid
.sink_data (hphy_bridge_s0_agent_rp_data), // .data
.sink_startofpacket (hphy_bridge_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hphy_bridge_s0_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_router_004 router_004 (
.sink_ready (sequencer_mem_s1_agent_rp_ready), // sink.ready
.sink_valid (sequencer_mem_s1_agent_rp_valid), // .valid
.sink_data (sequencer_mem_s1_agent_rp_data), // .data
.sink_startofpacket (sequencer_mem_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_mem_s1_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_router_003 router_005 (
.sink_ready (sequencer_scc_mgr_inst_avl_agent_rp_ready), // sink.ready
.sink_valid (sequencer_scc_mgr_inst_avl_agent_rp_valid), // .valid
.sink_data (sequencer_scc_mgr_inst_avl_agent_rp_data), // .data
.sink_startofpacket (sequencer_scc_mgr_inst_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_scc_mgr_inst_avl_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_router_006 router_006 (
.sink_ready (sequencer_reg_file_inst_avl_agent_rp_ready), // sink.ready
.sink_valid (sequencer_reg_file_inst_avl_agent_rp_valid), // .valid
.sink_data (sequencer_reg_file_inst_avl_agent_rp_data), // .data
.sink_startofpacket (sequencer_reg_file_inst_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_reg_file_inst_avl_agent_rp_endofpacket), // .endofpacket
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (92),
.PKT_DEST_ID_L (91),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (89),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (106),
.ST_CHANNEL_W (4),
.VALID_WIDTH (4),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) seq_bridge_m0_limiter (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (seq_bridge_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (seq_bridge_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (seq_bridge_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (seq_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (seq_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (seq_bridge_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (seq_bridge_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (seq_bridge_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (seq_bridge_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (seq_bridge_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (seq_bridge_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (seq_bridge_m0_limiter_cmd_valid_data) // cmd_valid.data
);
ddr3_s0_mm_interconnect_0_cmd_demux cmd_demux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (seq_bridge_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (seq_bridge_m0_limiter_cmd_src_channel), // .channel
.sink_data (seq_bridge_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (seq_bridge_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (seq_bridge_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (seq_bridge_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_cmd_mux cmd_mux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_demux_002_src0_valid), // .valid
.sink2_channel (cmd_demux_002_src0_channel), // .channel
.sink2_data (cmd_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_cmd_mux_003 cmd_mux_003 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_cmd_demux_002 rsp_demux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_001_src2_ready), // src2.ready
.src2_valid (rsp_demux_001_src2_valid), // .valid
.src2_data (rsp_demux_001_src2_data), // .data
.src2_channel (rsp_demux_001_src2_channel), // .channel
.src2_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_001_src2_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_cmd_demux_002 rsp_demux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_rsp_demux_003 rsp_demux_003 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_rsp_mux rsp_mux (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_003_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_003_src1_valid), // .valid
.sink1_channel (rsp_demux_003_src1_channel), // .channel
.sink1_data (rsp_demux_003_src1_data), // .data
.sink1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (avl_clk_out_clk_clk), // clk.clk
.reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src2_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src2_valid), // .valid
.sink0_channel (rsp_demux_001_src2_channel), // .channel
.sink0_data (rsp_demux_001_src2_data), // .data
.sink0_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src2_endofpacket) // .endofpacket
);
ddr3_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hphy_bridge_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hphy_bridge_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hphy_bridge_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
ddr3_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_mem_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_mem_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_mem_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
ddr3_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_scc_mgr_inst_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
ddr3_s0_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (avl_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_inst_reset_n_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sequencer_reg_file_inst_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
endmodule
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