189 lines
17 KiB
VHDL
189 lines
17 KiB
VHDL
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-- ddr3.vhd
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-- Generated using ACDS version 15.1 185
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity ddr3 is
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port (
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pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
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global_reset_n : in std_logic := '0'; -- global_reset.reset_n
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soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
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afi_clk : out std_logic; -- afi_clk.clk
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afi_half_clk : out std_logic; -- afi_half_clk.clk
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afi_reset_n : out std_logic; -- afi_reset.reset_n
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afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
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mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a
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mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
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mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck
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mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
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mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
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mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
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mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm
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mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
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mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
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mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
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mem_reset_n : out std_logic; -- .mem_reset_n
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mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq
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mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs
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mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n
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mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
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avl_ready_0 : out std_logic; -- avl_0.waitrequest_n
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avl_burstbegin_0 : in std_logic := '0'; -- .beginbursttransfer
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avl_addr_0 : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
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avl_rdata_valid_0 : out std_logic; -- .readdatavalid
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avl_rdata_0 : out std_logic_vector(31 downto 0); -- .readdata
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avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
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avl_be_0 : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
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avl_read_req_0 : in std_logic := '0'; -- .read
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avl_write_req_0 : in std_logic := '0'; -- .write
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avl_size_0 : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
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mp_cmd_clk_0_clk : in std_logic := '0'; -- mp_cmd_clk_0.clk
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mp_cmd_reset_n_0_reset_n : in std_logic := '0'; -- mp_cmd_reset_n_0.reset_n
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mp_rfifo_clk_0_clk : in std_logic := '0'; -- mp_rfifo_clk_0.clk
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mp_rfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_rfifo_reset_n_0.reset_n
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mp_wfifo_clk_0_clk : in std_logic := '0'; -- mp_wfifo_clk_0.clk
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mp_wfifo_reset_n_0_reset_n : in std_logic := '0'; -- mp_wfifo_reset_n_0.reset_n
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csr_clk : in std_logic := '0'; -- csr_clk.clk
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csr_reset_n : in std_logic := '0'; -- csr_reset_n.reset_n
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local_init_done : out std_logic; -- status.local_init_done
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local_cal_success : out std_logic; -- .local_cal_success
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local_cal_fail : out std_logic; -- .local_cal_fail
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oct_rzqin : in std_logic := '0'; -- oct.rzqin
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pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
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pll_write_clk : out std_logic; -- .pll_write_clk
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pll_locked : out std_logic; -- .pll_locked
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pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
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pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
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pll_avl_clk : out std_logic; -- .pll_avl_clk
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pll_config_clk : out std_logic; -- .pll_config_clk
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pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk
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afi_phy_clk : out std_logic; -- .afi_phy_clk
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pll_avl_phy_clk : out std_logic -- .pll_avl_phy_clk
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);
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end entity ddr3;
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architecture rtl of ddr3 is
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component ddr3_0002 is
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port (
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pll_ref_clk : in std_logic := 'X'; -- clk
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global_reset_n : in std_logic := 'X'; -- reset_n
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soft_reset_n : in std_logic := 'X'; -- reset_n
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afi_clk : out std_logic; -- clk
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afi_half_clk : out std_logic; -- clk
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afi_reset_n : out std_logic; -- reset_n
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afi_reset_export_n : out std_logic; -- reset_n
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mem_a : out std_logic_vector(12 downto 0); -- mem_a
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mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
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mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
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mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
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mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
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mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
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mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
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mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n
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mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n
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mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n
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mem_reset_n : out std_logic; -- mem_reset_n
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mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
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mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
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mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
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mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
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avl_ready_0 : out std_logic; -- waitrequest_n
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avl_burstbegin_0 : in std_logic := 'X'; -- beginbursttransfer
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avl_addr_0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
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avl_rdata_valid_0 : out std_logic; -- readdatavalid
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avl_rdata_0 : out std_logic_vector(31 downto 0); -- readdata
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avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
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avl_be_0 : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
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avl_read_req_0 : in std_logic := 'X'; -- read
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avl_write_req_0 : in std_logic := 'X'; -- write
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avl_size_0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
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mp_cmd_clk_0_clk : in std_logic := 'X'; -- clk
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mp_cmd_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n
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mp_rfifo_clk_0_clk : in std_logic := 'X'; -- clk
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mp_rfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n
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mp_wfifo_clk_0_clk : in std_logic := 'X'; -- clk
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mp_wfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n
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csr_clk : in std_logic := 'X'; -- clk
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csr_reset_n : in std_logic := 'X'; -- reset_n
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local_init_done : out std_logic; -- local_init_done
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local_cal_success : out std_logic; -- local_cal_success
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local_cal_fail : out std_logic; -- local_cal_fail
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oct_rzqin : in std_logic := 'X'; -- rzqin
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pll_mem_clk : out std_logic; -- pll_mem_clk
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pll_write_clk : out std_logic; -- pll_write_clk
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pll_locked : out std_logic; -- pll_locked
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pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
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pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
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pll_avl_clk : out std_logic; -- pll_avl_clk
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pll_config_clk : out std_logic; -- pll_config_clk
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pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
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afi_phy_clk : out std_logic; -- afi_phy_clk
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pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
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);
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end component ddr3_0002;
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begin
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ddr3_inst : component ddr3_0002
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port map (
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pll_ref_clk => pll_ref_clk, -- pll_ref_clk.clk
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global_reset_n => global_reset_n, -- global_reset.reset_n
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soft_reset_n => soft_reset_n, -- soft_reset.reset_n
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afi_clk => afi_clk, -- afi_clk.clk
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afi_half_clk => afi_half_clk, -- afi_half_clk.clk
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afi_reset_n => afi_reset_n, -- afi_reset.reset_n
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afi_reset_export_n => afi_reset_export_n, -- afi_reset_export.reset_n
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mem_a => mem_a, -- memory.mem_a
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mem_ba => mem_ba, -- .mem_ba
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mem_ck => mem_ck, -- .mem_ck
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mem_ck_n => mem_ck_n, -- .mem_ck_n
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mem_cke => mem_cke, -- .mem_cke
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mem_cs_n => mem_cs_n, -- .mem_cs_n
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mem_dm => mem_dm, -- .mem_dm
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mem_ras_n => mem_ras_n, -- .mem_ras_n
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mem_cas_n => mem_cas_n, -- .mem_cas_n
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mem_we_n => mem_we_n, -- .mem_we_n
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mem_reset_n => mem_reset_n, -- .mem_reset_n
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mem_dq => mem_dq, -- .mem_dq
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mem_dqs => mem_dqs, -- .mem_dqs
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mem_dqs_n => mem_dqs_n, -- .mem_dqs_n
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mem_odt => mem_odt, -- .mem_odt
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avl_ready_0 => avl_ready_0, -- avl_0.waitrequest_n
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avl_burstbegin_0 => avl_burstbegin_0, -- .beginbursttransfer
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avl_addr_0 => avl_addr_0, -- .address
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avl_rdata_valid_0 => avl_rdata_valid_0, -- .readdatavalid
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avl_rdata_0 => avl_rdata_0, -- .readdata
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avl_wdata_0 => avl_wdata_0, -- .writedata
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avl_be_0 => avl_be_0, -- .byteenable
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avl_read_req_0 => avl_read_req_0, -- .read
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avl_write_req_0 => avl_write_req_0, -- .write
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avl_size_0 => avl_size_0, -- .burstcount
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mp_cmd_clk_0_clk => mp_cmd_clk_0_clk, -- mp_cmd_clk_0.clk
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mp_cmd_reset_n_0_reset_n => mp_cmd_reset_n_0_reset_n, -- mp_cmd_reset_n_0.reset_n
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mp_rfifo_clk_0_clk => mp_rfifo_clk_0_clk, -- mp_rfifo_clk_0.clk
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mp_rfifo_reset_n_0_reset_n => mp_rfifo_reset_n_0_reset_n, -- mp_rfifo_reset_n_0.reset_n
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mp_wfifo_clk_0_clk => mp_wfifo_clk_0_clk, -- mp_wfifo_clk_0.clk
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mp_wfifo_reset_n_0_reset_n => mp_wfifo_reset_n_0_reset_n, -- mp_wfifo_reset_n_0.reset_n
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csr_clk => csr_clk, -- csr_clk.clk
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csr_reset_n => csr_reset_n, -- csr_reset_n.reset_n
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local_init_done => local_init_done, -- status.local_init_done
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local_cal_success => local_cal_success, -- .local_cal_success
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local_cal_fail => local_cal_fail, -- .local_cal_fail
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oct_rzqin => oct_rzqin, -- oct.rzqin
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pll_mem_clk => pll_mem_clk, -- pll_sharing.pll_mem_clk
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pll_write_clk => pll_write_clk, -- .pll_write_clk
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pll_locked => pll_locked, -- .pll_locked
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pll_write_clk_pre_phy_clk => pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk
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pll_addr_cmd_clk => pll_addr_cmd_clk, -- .pll_addr_cmd_clk
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pll_avl_clk => pll_avl_clk, -- .pll_avl_clk
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pll_config_clk => pll_config_clk, -- .pll_config_clk
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pll_mem_phy_clk => pll_mem_phy_clk, -- .pll_mem_phy_clk
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afi_phy_clk => afi_phy_clk, -- .afi_phy_clk
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pll_avl_phy_clk => pll_avl_phy_clk -- .pll_avl_phy_clk
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);
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end architecture rtl; -- of ddr3
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