24 lines
691 B
VHDL
24 lines
691 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.wishbone_package.all;
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package clock_crossing_package is
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component clock_crossing is
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generic(
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sync_depth : natural := 2;
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log2fifo : natural := 4);
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port(
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-- Common wishbone signals
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rst : in std_logic;
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-- Slave control port
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slave_clk : in std_logic;
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slave_i : in wishbone_slave_in;
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slave_o : out wishbone_slave_out;
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-- Master reader port
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master_clk : in std_logic;
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master_i : in wishbone_master_in;
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master_o : out wishbone_master_out);
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end component;
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end package;
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