32 lines
756 B
VHDL
32 lines
756 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity edgeDetector is
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port(
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clk : in std_logic;
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rst : in std_logic;
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sig : in std_logic;
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risingEdge : out std_logic;
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fallingEdge : out std_logic;
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anyEdge : out std_logic
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);
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end entity edgeDetector;
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architecture RTL of edgeDetector is
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signal temp : std_logic_vector(1 downto 0);
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begin
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shiftomat : process(rst, clk) is
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begin
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if rst = '1' then
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temp <= "00";
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elsif rising_edge(clk) then
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temp <= temp(0) & sig;
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end if;
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end process shiftomat;
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risingEdge <= '1' when (temp = "01") else '0';
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fallingEdge <= '1' when (temp = "10") else '0';
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anyEdge <= '1' when (temp = "01" or temp = "10") else '0';
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end architecture RTL;
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