322 lines
11 KiB
VHDL
322 lines
11 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library ddr3;
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library ip;
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use ip.wishbone_package.all;
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use ip.mor1kx_pkg.all;
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entity top is
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port(
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clk_hw : in std_logic;
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rst_hw : in std_logic;
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-- GPIO
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GPIOA : inout std_logic_vector(wishbone_data_width - 1 downto 0);
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-- JINN
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jinn_uart_rx : in std_logic;
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jinn_uart_tx : out std_logic;
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-- UART
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uart_rx : in std_logic;
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uart_tx : out std_logic;
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-- DDR3 RAM
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mem_a : out std_logic_vector(12 downto 0); -- memory.mem_a
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mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
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mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck
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mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n
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mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
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mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
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mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm
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mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
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mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
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mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
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mem_reset_n : out std_logic; -- .mem_reset_n
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mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq
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mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs
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mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n
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mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
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oct_rzqin : in std_logic -- oct.rzqin
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);
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end entity top;
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architecture RTL of top is
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constant debug_baud : natural := 460800;
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constant F_CPU : natural := 50000000;
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-- WB config
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constant masters : natural := 3;
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constant slaves : natural := 2;
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constant INTERCON_ID_SRAM : natural := 0;
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constant INTERCON_ID_DDR3 : natural := 1;
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constant INTERCON_ID_GPIO : natural := 2;
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constant INTERCON_ID_UART : natural := 3;
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constant INTERCON_ID_NS16550 : natural := 4;
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constant in_simulation : boolean := false
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--pragma synthesis_off
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or true
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--pragma synthesis_on
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;
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constant in_synthesis : boolean := not in_simulation;
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signal clk : std_logic;
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signal rst : std_logic;
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signal interrupt : std_logic_vector(32 - 1 downto 0);
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signal intercon_slave_i : wishbone_v3_slave_in_vector(slaves - 1 downto 0);
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signal intercon_slave_o : wishbone_v3_slave_out_vector(slaves - 1 downto 0);
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signal intercon_master_i : wishbone_v3_master_in_vector(masters - 1 downto 0);
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signal intercon_master_o : wishbone_v3_master_out_vector(masters - 1 downto 0);
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signal pll_locked : std_logic;
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signal rst_ddr3_n : std_logic;
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signal debug_o : debug_interface_o;
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signal debug_i : debug_interface_i;
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signal traceport_exec_valid_o : std_logic;
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signal traceport_exec_pc_o : std_logic_vector(31 downto 0);
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signal traceport_exec_insn_o : std_logic_vector(OR1K_INSN_WIDTH - 1 downto 0);
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signal traceport_exec_wbdata_o : std_logic_vector(OPTION_OPERAND_WIDTH - 1 downto 0);
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signal traceport_exec_wbreg_o : std_logic_vector(OPTION_RF_ADDR_WIDTH - 1 downto 0);
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signal traceport_exec_wben_o : std_logic;
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signal mor1kx_rst : std_logic;
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signal jinn_data_i : std_logic_vector(7 downto 0);
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signal jinn_data_available : std_logic;
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signal jinn_data_o : std_logic_vector(7 downto 0);
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signal jinn_data_valid_o : std_logic;
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signal jinn_uart_busy_i : std_logic;
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signal avl_ready_0 : std_logic;
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signal avl_burstbegin_0 : std_logic;
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signal avl_addr_0 : std_logic_vector(24 downto 0);
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signal avl_rdata_valid_0 : std_logic;
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signal avl_rdata_0 : std_logic_vector(31 downto 0);
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signal avl_wdata_0 : std_logic_vector(31 downto 0);
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signal avl_be_0 : std_logic_vector(3 downto 0);
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signal avl_read_req_0 : std_logic;
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signal avl_write_req_0 : std_logic;
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signal avl_size_0 : std_logic_vector(2 downto 0);
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signal local_init_done : std_logic; -- status.local_init_done
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signal local_cal_success : std_logic; -- .local_cal_success
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signal local_cal_fail : std_logic; -- .local_cal_fail
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signal avl_reqEn : std_logic;
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signal writeAck : std_logic;
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signal readAck : std_logic;
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begin
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debug_i.addr <= (others => '0');
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debug_i.dat <= (others => '0');
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debug_i.stb <= '1';
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debug_i.we <= '0';
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-- System controller
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resetSync : process(clk, rst_hw) is
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begin
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if rst_hw = '0' then -- low active
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rst <= '1';
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rst_ddr3_n <= '0';
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elsif rising_edge(clk) then
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if pll_locked = '1' then
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rst_ddr3_n <= '1'; -- Start DDR3 Controller
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if local_init_done = '1' and local_cal_success = '1' then
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rst <= '0'; -- Start system!
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end if;
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end if;
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end if;
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end process resetSync;
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-- Clock management
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clk <= clk_hw;
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pll_locked <= '1';
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-- SRAM
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sram_wb_inst : entity work.sram_wb
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port map(
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clk => clk,
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rst => rst,
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wb_in => intercon_slave_i(INTERCON_ID_SRAM),
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wb_out => intercon_slave_o(INTERCON_ID_SRAM)
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);
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-- CPU
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interrupt <= (others => '0');
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mor1kx_vhdl_inst : entity ip.mor1kx_vhdl
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port map(
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clk => clk,
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rst => mor1kx_rst,
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data_o => intercon_master_o(1),
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data_i => intercon_master_i(1),
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inst_o => intercon_master_o(0),
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inst_i => intercon_master_i(0),
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irq_i => interrupt,
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debug_o => debug_o,
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debug_i => debug_i,
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traceport_exec_valid_o => traceport_exec_valid_o,
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traceport_exec_pc_o => traceport_exec_pc_o,
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traceport_exec_insn_o => traceport_exec_insn_o,
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traceport_exec_wbdata_o => traceport_exec_wbdata_o,
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traceport_exec_wbreg_o => traceport_exec_wbreg_o,
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traceport_exec_wben_o => traceport_exec_wben_o
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);
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-- Debug interface
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jinn_inst : entity work.jinn
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port map(
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clk_i => clk,
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rst_i => rst,
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master_i => intercon_master_i(2),
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master_o => intercon_master_o(2),
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cpu_stall => debug_i.stall,
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cpu_reset => mor1kx_rst,
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data_i => jinn_data_i,
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data_available => jinn_data_available,
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data_o => jinn_data_o,
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data_valid_o => jinn_data_valid_o,
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output_busy_i => jinn_uart_busy_i
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);
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uart_rx_inst : entity work.uart_rx
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port map(
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clk => clk,
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rst => rst,
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data => jinn_data_i,
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byte_ready => jinn_data_available,
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error => open,
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ckDiv => std_logic_vector(to_unsigned(F_CPU / debug_baud - 1, 16)),
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parityEnable => '0',
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parityOdd => '0',
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twoStopBits => '0',
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rx => jinn_uart_rx
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);
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uart_tx_inst : entity work.uart_tx
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port map(
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clk => clk,
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rst => rst,
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data => jinn_data_o,
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byte_ready => jinn_data_valid_o,
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busy => jinn_uart_busy_i,
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ckDiv => std_logic_vector(to_unsigned(F_CPU / debug_baud - 1, 16)),
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parityEnable => '0',
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parityOdd => '0',
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twoStopBits => '0',
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tx => jinn_uart_tx
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);
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-- DDR3 RAM
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ddr3_inst : entity ddr3.ddr3
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port map(
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pll_ref_clk => clk,
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global_reset_n => rst_hw,
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soft_reset_n => '1',
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afi_clk => open,
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afi_half_clk => open,
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afi_reset_n => open,
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afi_reset_export_n => open,
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mem_a => mem_a,
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mem_ba => mem_ba,
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mem_ck => mem_ck,
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mem_ck_n => mem_ck_n,
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mem_cke => mem_cke,
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mem_cs_n => mem_cs_n,
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mem_dm => mem_dm,
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mem_ras_n => mem_ras_n,
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mem_cas_n => mem_cas_n,
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mem_we_n => mem_we_n,
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mem_reset_n => mem_reset_n,
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mem_dq => mem_dq,
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mem_dqs => mem_dqs,
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mem_dqs_n => mem_dqs_n,
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mem_odt => mem_odt,
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avl_ready_0 => avl_ready_0,
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avl_burstbegin_0 => avl_burstbegin_0,
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avl_addr_0 => avl_addr_0,
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avl_rdata_valid_0 => avl_rdata_valid_0,
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avl_rdata_0 => avl_rdata_0,
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avl_wdata_0 => avl_wdata_0,
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avl_be_0 => avl_be_0,
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avl_read_req_0 => avl_read_req_0,
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avl_write_req_0 => avl_write_req_0,
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avl_size_0 => avl_size_0,
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mp_cmd_clk_0_clk => clk,
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mp_cmd_reset_n_0_reset_n => rst_hw,
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mp_rfifo_clk_0_clk => clk,
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mp_rfifo_reset_n_0_reset_n => rst_hw,
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mp_wfifo_clk_0_clk => clk,
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mp_wfifo_reset_n_0_reset_n => rst_hw,
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local_init_done => local_init_done,
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local_cal_success => local_cal_success,
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local_cal_fail => local_cal_fail,
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oct_rzqin => oct_rzqin,
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pll_mem_clk => open,
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pll_write_clk => open,
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pll_locked => open,
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pll_write_clk_pre_phy_clk => open,
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pll_addr_cmd_clk => open,
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pll_avl_clk => open,
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pll_config_clk => open,
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pll_mem_phy_clk => open,
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afi_phy_clk => open,
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pll_avl_phy_clk => open,
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csr_clk => clk,
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csr_reset_n => rst_hw
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);
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avl_addr_0 <= intercon_slave_i(INTERCON_ID_DDR3).ADR(26 downto 2); -- & "00";
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avl_be_0 <= intercon_slave_i(INTERCON_ID_DDR3).SEL;
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avl_burstbegin_0 <= '0';
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avl_wdata_0 <= intercon_slave_i(INTERCON_ID_DDR3).DAT;
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avl_read_req_0 <= (intercon_slave_i(INTERCON_ID_DDR3).STB and (not intercon_slave_i(INTERCON_ID_DDR3).WE)) and avl_reqEn;
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avl_write_req_0 <= (intercon_slave_i(INTERCON_ID_DDR3).STB and intercon_slave_i(INTERCON_ID_DDR3).WE) and avl_reqEn;
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avl_size_0 <= "001";
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intercon_slave_o(INTERCON_ID_DDR3).DAT <= avl_rdata_0;
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intercon_slave_o(INTERCON_ID_DDR3).ERR <= '0';
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intercon_slave_o(INTERCON_ID_DDR3).RTY <= '0';
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intercon_slave_o(INTERCON_ID_DDR3).ACK <= (readAck or writeAck) and intercon_slave_i(INTERCON_ID_DDR3).STB;
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readAck <= avl_rdata_valid_0; --(avl_rdata_valid_0 and not intercon_slave_i(INTERCON_ID_SRAM).WE);
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writeAck <= (intercon_slave_i(INTERCON_ID_DDR3).WE and avl_ready_0);
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wb2avl : process(clk, rst) is
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begin
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if rst = '1' then
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avl_reqEn <= '1';
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elsif rising_edge(clk) then
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if intercon_slave_i(INTERCON_ID_DDR3).STB = '1' then
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avl_reqEn <= '0';
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else
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avl_reqEn <= '1';
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end if;
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end if;
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end process wb2avl;
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-- Intercon
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crossbar_inst : entity ip.crossbar
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generic map(
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masters => masters,
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slaves => slaves,
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async => true
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)
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port map(
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clk => clk,
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rst => rst,
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slave_i => intercon_master_o,
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slave_o => intercon_master_i,
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master_i => intercon_slave_o,
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master_o => intercon_slave_i,
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address => (0 => x"00000000", -- SRAM
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1 => x"80000000"
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),
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mask => (0 => x"ffff0000",
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1 => x"f0000000"
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)
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);
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end architecture RTL;
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