fpga/mor1kx-bemicrocv
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flashrom: Minor changes

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This commit is contained in:
Markus Koch 2016-12-10 20:48:43 +01:00
parent 054ae0e210
commit 9051e3385b
4 changed files with 6 additions and 6 deletions
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2
bench/bench_flashrom_controller.vhd
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@ -33,7 +33,7 @@ architecture rtl of bench_flashrom_controller is
end procedure strobe; end procedure strobe;
signal clr : std_logic; signal clr : std_logic;
signal ready : std_logic; signal ready : std_logic;
signal page : std_logic_vector(FLASHROM_ADDR_WIDTH - 1 downto 0); signal page : std_logic_vector(FLASHROM_PAGE_ADDR_WIDTH - 1 downto 0);
signal sync_stb : std_logic; signal sync_stb : std_logic;
signal load_stb : std_logic; signal load_stb : std_logic;
signal status_update_stb : std_logic; signal status_update_stb : std_logic;

4
cores/flashrom-wb/flashrom_controller.vhd
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@ -12,7 +12,7 @@ entity flashrom_controller is
-- Control IF -- Control IF
ready : out std_logic; -- The controller is ready to accept commands ready : out std_logic; -- The controller is ready to accept commands
page : in std_logic_vector(FLASHROM_ADDR_WIDTH - 1 downto 0); page : in std_logic_vector(FLASHROM_PAGE_ADDR_WIDTH - 1 downto 0);
sync_stb : in std_logic; -- Synchronize current memory page with chip, only sampled when ready sync_stb : in std_logic; -- Synchronize current memory page with chip, only sampled when ready
load_stb : in std_logic; -- Load page into local buffer, only sampled when ready load_stb : in std_logic; -- Load page into local buffer, only sampled when ready
status_update_stb : in std_logic; -- Update status vector status_update_stb : in std_logic; -- Update status vector
@ -28,7 +28,7 @@ entity flashrom_controller is
-- SPI flash hardware signals -- SPI flash hardware signals
spi_si : out std_logic; -- SPI serial in spi_si : out std_logic; -- SPI serial in
spi_so : in std_logic; -- SPI serial out spi_so : in std_logic; -- SPI serial out
spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module spi_sck : out std_logic; -- SPI clock
spi_reset_n : out std_logic; -- SPI hard reset spi_reset_n : out std_logic; -- SPI hard reset
spi_cs_n : out std_logic; -- SPI chip select spi_cs_n : out std_logic; -- SPI chip select
spi_wp_n : out std_logic -- SPI write protect spi_wp_n : out std_logic -- SPI write protect

2
cores/flashrom-wb/flashrom_pkg.vhd
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@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
package flashrom_pkg is package flashrom_pkg is
constant FLASHROM_ADDR_WIDTH : integer := 12; constant FLASHROM_PAGE_ADDR_WIDTH : integer := 12;
constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F"; constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F";
constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7"; constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7";
constant FLASHROM_COMMAND_CONT_ARRAY_READ : std_logic_vector(7 downto 0) := x"0B"; constant FLASHROM_COMMAND_CONT_ARRAY_READ : std_logic_vector(7 downto 0) := x"0B";

2
cores/flashrom-wb/flashrom_spi.vhd
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@ -16,7 +16,7 @@ entity flashrom_spi is
-- SPI flash hardware signals -- SPI flash hardware signals
spi_si : out std_logic; -- SPI serial in spi_si : out std_logic; -- SPI serial in
spi_so : in std_logic; -- SPI serial out spi_so : in std_logic; -- SPI serial out
spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module spi_sck : out std_logic; -- SPI clock
spi_cs_n : out std_logic; -- SPI chip select spi_cs_n : out std_logic; -- SPI chip select
-- Logic interface -- Logic interface