fpga/mor1kx-bemicrocv
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Rewrote SPI PHY -> Flash ROM works now

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This commit is contained in:
Markus Koch 2017-03-01 19:08:01 +01:00
parent b48571db24
commit c649c073ce
8 changed files with 106 additions and 353 deletions
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18
bench/bench_flashrom_wb.vhd
View File

@ -42,6 +42,7 @@ architecture RTL of bench_flashrom_wb is
s <= '0'; s <= '0';
waitclk; waitclk;
end procedure strobe; end procedure strobe;
signal slave_rx_data : std_logic_vector(7 downto 0);
begin begin
DataFlash_inst : entity work.DataFlash DataFlash_inst : entity work.DataFlash
generic map( generic map(
@ -101,6 +102,7 @@ begin
wb_in.STB <= '1'; wb_in.STB <= '1';
wb_in.WE <= '0'; wb_in.WE <= '0';
wait until wb_out.ACK = '1'; wait until wb_out.ACK = '1';
waitclk;
wb_in.CYC <= '0'; wb_in.CYC <= '0';
wb_in.STB <= '0'; wb_in.STB <= '0';
waitnclk(DEL); waitnclk(DEL);
@ -113,7 +115,7 @@ begin
waitclk; waitclk;
wb_in.CYC <= '0'; wb_in.CYC <= '0';
wb_in.STB <= '0'; wb_in.STB <= '0';
waitnclk(22); --waitnclk(22); -- Time after read to write needs to be longer waitnclk(DEL); --waitnclk(22); -- Time after read to write needs to be longer (was bug)
wb_in.ADR <= std_logic_vector(to_unsigned(4, 32)); wb_in.ADR <= std_logic_vector(to_unsigned(4, 32));
wb_in.DAT <= x"deadbeef"; wb_in.DAT <= x"deadbeef";
@ -220,4 +222,18 @@ begin
wait; wait;
end process test; end process test;
slave_rx : process is
variable data : std_logic_vector(7 downto 0);
begin
wait until spi_cs_n = '0';
while true loop
for i in 7 downto 0 loop
wait until spi_sck = '1';
data(i) := spi_si;
end loop;
slave_rx_data <= data;
end loop;
end process slave_rx;
end architecture RTL; end architecture RTL;

42
cores/flashrom-wb/flashrom_controller.vhd
View File

@ -54,33 +54,37 @@ architecture RTL of flashrom_controller is
signal words_sent : integer range 0 to 511; signal words_sent : integer range 0 to 511;
signal spif_data_out_dummy_bits : integer range 0 to max_dummy_bits; signal spif_data_out_dummy_bits : integer range 0 to max_dummy_bits;
signal spif_transmission_active : std_logic;
signal command_is_latched : boolean; signal command_is_latched : boolean;
begin begin
spi_wp_n <= '1'; spi_wp_n <= '1';
flashrom_spi_inst : entity work.flashrom_spi fancy_spi_master_inst : entity work.fancy_spi_master
generic map( generic map(
clk_divider => 4, TX_WIDTH_MAX => spif_max_word_length,
max_word_length => spif_max_word_length, RX_WIDTH_MAX => spif_max_word_length,
max_dummy_bits => max_dummy_bits) RX_IGNORE_MAX => max_dummy_bits + 400,
SPI_CPOL => '0',
SPI_CPHA => '0',
CKDIV => 8,
CS_INACTIVE_DELAY => 400
)
port map( port map(
clk => clk, clk => clk,
rst => rst, rst => rst,
clr => clr, clr => clr,
spi_si => spi_si, tx_width => spif_data_in_length,
spi_so => spi_so, tx_enable => spif_data_in_valid,
spi_sck => spi_sck, tx_data => spif_data_in,
tx_next => spif_data_next,
rx_width => spif_data_out_length,
rx_valid => spif_data_out_valid,
rx_data => spif_data_out,
rx_ignore => spif_data_out_dummy_bits,
spi_clk => spi_sck,
spi_cs_n => spi_cs_n, spi_cs_n => spi_cs_n,
data_in_valid => spif_data_in_valid, spi_mosi => spi_si,
data_in => spif_data_in, spi_miso => spi_so
data_in_length => spif_data_in_length, );
data_next => spif_data_next,
data_out => spif_data_out,
data_out_valid => spif_data_out_valid,
data_out_length => spif_data_out_length,
data_out_dummy_bits => spif_data_out_dummy_bits,
transmission_active => spif_transmission_active);
flashrom_controller_p : process(clk, rst) is flashrom_controller_p : process(clk, rst) is
variable write_cnt : integer range 0 to bootup_delay; variable write_cnt : integer range 0 to bootup_delay;
@ -190,7 +194,7 @@ begin
delay_cnt := delay_cnt + 1; delay_cnt := delay_cnt + 1;
end if; end if;
when LOADPAGE => when LOADPAGE =>
run_command_single(32, 8, 40, 259, FLASHROM_COMMAND_CONT_ARRAY_READ & page); run_command_single(32, 8, 40, 258, FLASHROM_COMMAND_CONT_ARRAY_READ & page);
if spif_data_next = '1' or command_is_latched then if spif_data_next = '1' or command_is_latched then
command_is_latched <= true; command_is_latched <= true;
spif_data_in_length <= 8; spif_data_in_length <= 8;
@ -200,7 +204,7 @@ begin
report "Load page done." severity note; report "Load page done." severity note;
end if; end if;
when WRITEPAGE => when WRITEPAGE =>
run_command_single(32, 8, 34, 257, FLASHROM_COMMAND_WRITE_THROUGH_1 & page); run_command_single(32, 8, 40, 257, FLASHROM_COMMAND_WRITE_THROUGH_1 & page);
if spif_data_next = '1' or command_is_latched then if spif_data_next = '1' or command_is_latched then
command_is_latched <= true; command_is_latched <= true;
spif_data_in_length <= 8; spif_data_in_length <= 8;

177
cores/flashrom-wb/flashrom_spi.vhd
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@ -1,177 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flashrom_spi is
generic(
clk_divider : integer range 2 to 9999 := 2;
max_word_length : integer := 32;
max_dummy_bits : integer := 8;
cs_inactive_cycles : integer := 10
);
port(
clk : in std_logic;
rst : in std_logic;
clr : in std_logic;
-- SPI flash hardware signals
spi_si : out std_logic; -- SPI serial in
spi_so : in std_logic; -- SPI serial out
spi_sck : out std_logic; -- SPI clock
spi_cs_n : out std_logic; -- SPI chip select
-- Logic interface
data_in_valid : in std_logic; -- Data to Flash ROM
data_in : in std_logic_vector(max_word_length - 1 downto 0);
data_in_length : in integer range 0 to max_word_length;
data_next : out std_logic;
data_out : out std_logic_vector(max_word_length - 1 downto 0);
data_out_valid : out std_logic; -- Data from Flash ROM
data_out_length : in integer range 0 to max_word_length;
data_out_dummy_bits : in integer range 0 to max_dummy_bits;
transmission_active : out std_logic
);
end entity flashrom_spi;
architecture RTL of flashrom_spi is
type txstate_t is (IDLE, TX);
signal state : txstate_t;
signal ckDiv : integer range 0 to clk_divider - 2;
signal shiftreg : std_logic_vector(max_word_length - 1 downto 0);
signal bitCounter : integer range 0 to max_word_length - 1;
signal bitCounterIn : integer range 0 to max_word_length + max_dummy_bits - 1; -- TODO: Actually this must count until the higher of the two
signal data_in_length_i : integer range 0 to max_word_length;
signal data_out_length_i : integer range 0 to max_word_length;
signal delayCycle : std_logic;
signal oneBitRead : std_logic;
signal pseudoEdge : boolean;
signal dummy_passed : boolean;
signal prevent_retrig : boolean;
signal cs_inactive_cnt : integer range 0 to cs_inactive_cycles;
begin
toSpi : process(clk, rst) is
procedure default_state is
begin
data_next <= '0';
data_out_valid <= '0';
pseudoEdge <= false;
cs_inactive_cnt <= 0;
end procedure default_state;
procedure reset_state is
begin
state <= IDLE;
spi_sck <= '0';
shiftreg <= (others => '0');
bitCounter <= 0;
bitCounterIn <= 0;
data_out <= (others => '0');
delayCycle <= '0';
oneBitRead <= '0';
dummy_passed <= false;
default_state;
end procedure reset_state;
begin
if rst = '1' then
reset_state;
elsif rising_edge(clk) then
default_state;
if clr = '1' then
reset_state;
else
case state is
when IDLE =>
cs_inactive_cnt <= cs_inactive_cnt;
prevent_retrig <= false;
delayCycle <= '0';
spi_sck <= '0';
oneBitRead <= '0';
dummy_passed <= false;
data_out <= (others => '0');
if ckDiv = clk_divider - 2 then -- ensures cs inactive time between transactions
if cs_inactive_cnt = cs_inactive_cycles then
if data_in_valid = '1' then
ckDiv <= 0;
state <= TX;
bitCounter <= 0;
bitCounterIn <= 0;
data_in_length_i <= 0;
pseudoEdge <= true;
end if;
else
ckDiv <= 0;
cs_inactive_cnt <= cs_inactive_cnt + 1;
end if;
else
ckDiv <= ckDiv + 1;
end if;
when TX =>
if data_in_valid = '0' then
prevent_retrig <= true;
end if;
if ckDiv = clk_divider - 2 or pseudoEdge then
ckDiv <= 0;
if not pseudoEdge then
spi_sck <= not spi_sck;
end if;
if spi_sck = '0' and bitCounter = data_in_length_i and data_in_valid = '0' then
-- Prevent last clock cycle (make it a "passive" one)
spi_sck <= '0';
pseudoEdge <= true;
end if;
if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data
if bitCounter = data_in_length_i then
bitCounter <= 0;
if data_in_valid = '1' and not prevent_retrig then
shiftreg <= data_in;
data_in_length_i <= data_in_length - 1;
data_out_length_i <= data_out_length - 1;
data_next <= '1';
else
delayCycle <= '1';
pseudoEdge <= true;
end if;
else
bitCounter <= bitCounter + 1;
shiftreg <= shiftreg(shiftreg'high - 1 downto 0) & '0';
end if;
--else -- spi_sck = '1' (falling edge)
data_out <= data_out(data_out'high - 1 downto 0) & spi_so;
if bitCounterIn = 0 then
if dummy_passed then
data_out_valid <= '1';
end if;
end if;
if not dummy_passed then
if bitCounterIn = data_out_dummy_bits then
dummy_passed <= true;
bitCounterIn <= 1;
else
bitCounterIn <= bitCounterIn + 1;
end if;
else
if bitCounterIn = data_out_length_i then
bitCounterIn <= 0;
else
bitCounterIn <= bitCounterIn + 1;
end if;
if delayCycle = '1' then
spi_sck <= '0';
state <= IDLE;
ckDiv <= 0;
end if;
end if;
end if;
else
ckDiv <= ckDiv + 1;
end if;
end case;
end if;
end if;
end process toSpi;
spi_si <= shiftreg(shiftreg'high);
spi_cs_n <= '0' when state = TX else '1';
transmission_active <= '1' when state = TX else '0';
end architecture RTL;

141
cores/flashrom-wb/flashrom_spi2.copyvhd
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@ -1,141 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flashrom_spi is
generic(
clk_divider : integer range 2 to 9999 := 2;
max_word_length : integer := 32;
max_dummy_bits : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
clr : in std_logic;
-- SPI flash hardware signals
spi_si : out std_logic; -- SPI serial in
spi_so : in std_logic; -- SPI serial out
spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module
spi_cs_n : out std_logic; -- SPI chip select
-- Logic interface
data_in_valid : in std_logic;
data_in : in std_logic_vector(max_word_length - 1 downto 0);
data_in_length : in integer range 0 to max_word_length;
data_next : out std_logic;
data_out : out std_logic_vector(max_word_length - 1 downto 0);
data_out_valid : out std_logic;
data_out_length : in integer range 0 to max_word_length;
data_out_dummy_bits : in integer range 0 to max_dummy_bits;
transmission_active : out std_logic
);
end entity flashrom_spi;
architecture RTL of flashrom_spi is
type txstate_t is (IDLE, TX);
signal state : txstate_t;
signal ckDiv : integer range 0 to clk_divider - 2;
signal shiftreg : std_logic_vector(max_word_length - 1 downto 0);
signal bitCounter : integer range 0 to max_word_length - 1;
signal bitCounterIn : integer range 0 to max_word_length + max_dummy_bits - 1;
signal data_in_length_i : integer range 0 to max_word_length;
signal data_out_length_i : integer range 0 to max_word_length;
signal delayCycle : std_logic;
signal oneBitRead : std_logic;
signal dummy_passed : boolean;
begin
toSpi : process(clk, rst) is
procedure default_state is
begin
data_next <= '0';
data_out_valid <= '0';
end procedure default_state;
procedure reset_state is
begin
state <= IDLE;
spi_sck <= '0';
shiftreg <= (others => '0');
bitCounter <= 0;
bitCounterIn <= 0;
data_out <= (others => '0');
delayCycle <= '0';
oneBitRead <= '0';
dummy_passed <= false;
default_state;
end procedure reset_state;
begin
if rst = '1' then
reset_state;
elsif rising_edge(clk) then
default_state;
if clr = '1' then
reset_state;
else
case state is
when IDLE =>
delayCycle <= '0';
spi_sck <= '0';
oneBitRead <= '0';
dummy_passed <= false;
data_out <= (others => '0');
if data_in_valid = '1' then
state <= TX;
bitCounter <= 0;
bitCounterIn <= 0;
data_in_length_i <= 0;
end if;
when TX =>
if ckDiv = clk_divider - 2 then
spi_sck <= not spi_sck;
if spi_sck = '0' then -- rising edge
if bitCounter = data_in_length_i then
bitCounter <= 0;
if data_in_valid = '1' then
shiftreg <= data_in;
data_in_length_i <= data_in_length - 1;
data_out_length_i <= data_out_length - 1;
data_next <= '1';
else
delayCycle <= '1';
end if;
else
bitCounter <= bitCounter + 1;
shiftreg <= shiftreg(shiftreg'high - 1 downto 0) & '0';
end if;
else -- spi_sck = '1' (falling edge)
data_out <= data_out(data_out'high - 1 downto 0) & spi_so;
oneBitRead <= '1';
if bitCounterIn = 0 then
if dummy_passed then
data_out_valid <= '1';
end if;
end if;
if not dummy_passed and bitCounterIn = data_out_dummy_bits then
dummy_passed <= true;
bitCounterIn <= 1;
else
if bitCounterIn = data_out_length_i then
bitCounterIn <= 0;
else
bitCounterIn <= bitCounterIn + 1;
end if;
if delayCycle = '1' then
spi_sck <= '0';
state <= IDLE;
end if;
end if;
end if;
else
ckDiv <= ckDiv + 1;
end if;
end case;
end if;
end if;
end process toSpi;
spi_si <= shiftreg(shiftreg'high);
spi_cs_n <= '0' when state = TX else '1';
transmission_active <= '1' when state = TX else '0';
end architecture RTL;

3
cores/flashrom-wb/flashrom_wb.vhd
View File

@ -200,4 +200,7 @@ begin
cache_addr <= wb_in.ADR(7 downto 0) when (state = IDLE and cache_we = '0') else std_logic_vector(cache_control_addr); cache_addr <= wb_in.ADR(7 downto 0) when (state = IDLE and cache_we = '0') else std_logic_vector(cache_control_addr);
wb_out.DAT <= cache_dOut; wb_out.DAT <= cache_dOut;
status_update_stb <= '0';
end architecture rtl; end architecture rtl;

14
quartus/mor1kx-bemicrocv.qsf
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@ -315,6 +315,19 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "1.5 V" -to rst_hw set_instance_assignment -name IO_STANDARD "1.5 V" -to rst_hw
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_location_assignment PIN_U10 -to flash_cs_n
set_location_assignment PIN_T9 -to flash_reset_n
set_location_assignment PIN_N16 -to flash_sck
set_location_assignment PIN_M16 -to flash_si
set_location_assignment PIN_M18 -to flash_so
set_location_assignment PIN_N19 -to flash_wp_n
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VHDL_FILE ../cores/generic/fancy_spi_master.vhd
set_global_assignment -name VHDL_FILE "../cores/flashrom-wb/flashrom_wb.vhd"
set_global_assignment -name VHDL_FILE "../cores/flashrom-wb/flashrom_pkg.vhd"
set_global_assignment -name VHDL_FILE "../cores/flashrom-wb/flashrom_controller.vhd"
set_global_assignment -name SDC_FILE "mor1kx-bemicrocv.out.sdc" set_global_assignment -name SDC_FILE "mor1kx-bemicrocv.out.sdc"
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_espresso.v" -library mor1kx set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_espresso.v" -library mor1kx
set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_cappuccino.v" -library mor1kx set_global_assignment -name VERILOG_FILE "../ip/mor1kx-mor1kx_v4/rtl/verilog/mor1kx_wb_mux_cappuccino.v" -library mor1kx
@ -368,4 +381,3 @@ set_global_assignment -name VHDL_FILE ../design/top.vhd
set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/wishbone_package.vhd -library ip set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/wishbone_package.vhd -library ip
set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/crossbar_v3.vhd -library ip set_global_assignment -name VHDL_FILE ../ip/intercon/rtl/crossbar_v3.vhd -library ip
set_global_assignment -name QIP_FILE ../ip/altera/ddr3.qip set_global_assignment -name QIP_FILE ../ip/altera/ddr3.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
quartus/mor1kx-bemicrocv.qws
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Binary file not shown.

40
wave/flashrom_wb.do
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@ -69,8 +69,44 @@ add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/max_dummy_bits add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/max_dummy_bits
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/bootup_delay add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/bootup_delay
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/status_reg_poll_delay add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/status_reg_poll_delay
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/TX_WIDTH_MAX
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/RX_WIDTH_MAX
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/RX_IGNORE_MAX
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/SPI_CPOL
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/SPI_CPHA
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/CKDIV
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/CS_INACTIVE_DELAY
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/clk
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/rst
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/clr
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/tx_width
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/tx_enable
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/tx_data
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/tx_next
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/rx_width
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/rx_valid
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/rx_data
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/rx_ignore
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/spi_clk
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/spi_cs_n
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/spi_mosi
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/spi_miso
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/spi_clk_en
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/spi_clk_i
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/ckdiv_cnt
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/spi_clk_event
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/state
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/tx_width_i
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/shiftreg_out
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/shiftreg_in
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/bit_cnt_tx
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/bit_cnt_rx
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/rx_past_ignore
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/rx_width_i
add wave -noupdate -expand -group phy /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/fancy_spi_master_inst/active_cycles
add wave -noupdate /bench_flashrom_wb/slave_rx_data
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {182209 ns} 0} WaveRestoreCursors {{Cursor 1} {39914 ns} 0}
quietly wave cursor active 1 quietly wave cursor active 1
configure wave -namecolwidth 173 configure wave -namecolwidth 173
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
@ -86,4 +122,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {168208 ns} {199740 ns} WaveRestoreZoom {39740 ns} {41430 ns}