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flashrom: Transmitted one clock cycle too long -> buffer shifted

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This commit is contained in:
Markus Koch 2016-12-04 17:58:01 +01:00
parent b01f74648e
commit e66c98a670
1 changed files with 7 additions and 1 deletions
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6
cores/flashrom-wb/flashrom_spi.vhd
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@ -92,9 +92,15 @@ begin
ckDiv <= 0; ckDiv <= 0;
when TX => when TX =>
if ckDiv = clk_divider - 2 or pseudoEdge then if ckDiv = clk_divider - 2 or pseudoEdge then
ckDiv <= 0;
if not pseudoEdge then if not pseudoEdge then
spi_sck <= not spi_sck; spi_sck <= not spi_sck;
end if; end if;
if spi_sck = '0' and bitCounter = data_in_length_i and data_in_valid = '0' then
-- Prevent last clock cycle (make it a "passive" one)
spi_sck <= '0';
pseudoEdge <= true;
end if;
if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data
if bitCounter = data_in_length_i then if bitCounter = data_in_length_i then
bitCounter <= 0; bitCounter <= 0;