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| @ -37,7 +37,7 @@ architecture rtl of bench_flashrom_controller is | ||||
| 	signal sync_stb          : std_logic; | ||||
| 	signal load_stb          : std_logic; | ||||
| 	signal status_update_stb : std_logic; | ||||
| 	signal status            : std_logic_vector(7 downto 0); | ||||
| 	signal status            : std_logic_vector(31 downto 0); | ||||
| 	signal info              : std_logic_vector(31 downto 0); | ||||
| 	signal data_in           : std_logic_vector(7 downto 0); | ||||
| 	signal data_in_valid     : std_logic; | ||||
| @ -50,7 +50,6 @@ architecture rtl of bench_flashrom_controller is | ||||
| 	signal spi_cs_n          : std_logic; | ||||
| 	signal spi_wp_n          : std_logic; | ||||
| 	signal spi_busy          : std_logic; | ||||
| 	signal spi_clk_cnt       : integer := 0; | ||||
| 
 | ||||
| begin | ||||
| 	DataFlash_inst : entity work.DataFlash | ||||
| @ -58,7 +57,7 @@ begin | ||||
| 			flashmemory     => "devicemodels/memory.txt", | ||||
| 			Rapid_interface => true, | ||||
| 			fsck            => 66, | ||||
| 			DEVICE          => "AT45DB011D", --AT45DB011D | ||||
| 			DEVICE          => "AT45DB011D", | ||||
| 			Tsck            => 13.6 ns) | ||||
| 		port map( | ||||
| 			SI     => spi_si, | ||||
| @ -116,30 +115,9 @@ begin | ||||
| 		wait until (rising_edge(clk)); | ||||
| 
 | ||||
| 		-- bench code here | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(load_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(load_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(status_update_stb); | ||||
| 
 | ||||
| 		wait until ready = '1'; | ||||
| 		strobe(load_stb); | ||||
| 		wait; | ||||
| 	end process bench; | ||||
| 
 | ||||
| 	spiclkcounter : process is | ||||
| 	begin | ||||
| 		wait until spi_sck = '1'; | ||||
| 		spi_clk_cnt <= spi_clk_cnt + 1; | ||||
| 	end process spiclkcounter; | ||||
| 
 | ||||
| end architecture rtl; | ||||
|  | ||||
| @ -16,7 +16,7 @@ entity flashrom_controller is | ||||
| 		sync_stb          : in  std_logic; -- Synchronize current memory page with chip, only sampled when ready | ||||
| 		load_stb          : in  std_logic; -- Load page into local buffer, only sampled when ready | ||||
| 		status_update_stb : in  std_logic; -- Update status vector | ||||
| 		status            : out std_logic_vector(7 downto 0); -- value of the status register (update using status_update_stb)  | ||||
| 		status            : out std_logic_vector(31 downto 0); -- value of the status register (update using status_update_stb)  | ||||
| 		info              : out std_logic_vector(31 downto 0); -- value of the information register (updated on reset) | ||||
| 
 | ||||
| 		-- Data IF		 | ||||
| @ -40,7 +40,7 @@ architecture RTL of flashrom_controller is | ||||
| 	constant max_dummy_bits       : integer := 16; | ||||
| 	constant bootup_delay         : integer := 4000; | ||||
| 
 | ||||
| 	type state_t is (INIT, GETINFO, GETSTATUS, IDLE); | ||||
| 	type state_t is (INIT, GETINFO, IDLE); | ||||
| 	signal state : state_t; | ||||
| 
 | ||||
| 	signal spif_data_in_valid   : std_logic; | ||||
| @ -59,7 +59,7 @@ begin | ||||
| 
 | ||||
| 	flashrom_spi_inst : entity work.flashrom_spi | ||||
| 		generic map( | ||||
| 			clk_divider     => 4, | ||||
| 			clk_divider     => 2, | ||||
| 			max_word_length => spif_max_word_length, | ||||
| 			max_dummy_bits  => max_dummy_bits) | ||||
| 		port map( | ||||
| @ -82,13 +82,11 @@ begin | ||||
| 
 | ||||
| 	flashrom_controller_p : process(clk, rst) is | ||||
| 		variable temp_cnt : integer range 0 to bootup_delay; | ||||
| 		variable done     : boolean; | ||||
| 
 | ||||
| 		procedure default_state is | ||||
| 		begin | ||||
| 			spi_reset_n        <= '1'; | ||||
| 			spif_data_in_valid <= '0'; | ||||
| 			done               := false; | ||||
| 		end procedure default_state; | ||||
| 
 | ||||
| 		procedure reset_state is | ||||
| @ -105,29 +103,6 @@ begin | ||||
| 
 | ||||
| 			temp_cnt := 0; | ||||
| 		end procedure reset_state; | ||||
| 
 | ||||
| 		procedure run_command_single(constant data_in_length : integer; constant data_out_length : integer; constant data_out_dummy_bits : integer; constant nTxWords : integer; constant data_in : std_logic_vector(31 downto 0)) is | ||||
| 		begin | ||||
| 			spif_data_in_length      <= data_in_length; | ||||
| 			spif_data_out_length     <= data_out_length; | ||||
| 			spif_data_out_dummy_bits <= data_out_dummy_bits; | ||||
| 			spif_data_in_valid       <= '1'; | ||||
| 			spif_data_in             <= data_in; | ||||
| 
 | ||||
| 			if temp_cnt = nTxWords then | ||||
| 				spif_data_in_valid <= '0'; | ||||
| 			elsif spif_data_next = '1' then | ||||
| 				temp_cnt := temp_cnt + 1; | ||||
| 			end if; | ||||
| 
 | ||||
| 			if spif_data_out_valid = '1' then | ||||
| 				spif_data_in_valid <= '0'; | ||||
| 				done               := true; | ||||
| 				state              <= IDLE; | ||||
| 				temp_cnt           := 0; | ||||
| 			end if; | ||||
| 		end procedure run_command_single; | ||||
| 
 | ||||
| 	begin | ||||
| 		if rst = '1' then | ||||
| 			reset_state; | ||||
| @ -145,27 +120,24 @@ begin | ||||
| 						else | ||||
| 							temp_cnt := temp_cnt + 1; | ||||
| 						end if; | ||||
| 					when GETINFO =>     -- TODO: In simulation I can only call this command once?! | ||||
| 						run_command_single(8, 32, 8, 5, FLASHROM_COMMAND_MANUFACTURER_ID & padBits(spif_data_in, FLASHROM_COMMAND_MANUFACTURER_ID)); | ||||
| 						if done then | ||||
| 					when GETINFO => | ||||
| 						spif_data_in_length      <= 8; -- Other bits after OpCode are don't care, so just repeat OPC | ||||
| 						spif_data_out_length     <= 32; | ||||
| 						spif_data_out_dummy_bits <= 8; | ||||
| 						spif_data_in_valid       <= '1'; | ||||
| 						spif_data_in             <= FLASHROM_COMMAND_MANUFACTURER_ID & padBits(spif_data_in, FLASHROM_COMMAND_MANUFACTURER_ID); | ||||
| 						if spif_data_out_valid = '1' then | ||||
| 							info  <= spif_data_out; | ||||
| 							state <= IDLE; | ||||
| 						end if; | ||||
| 					when IDLE => | ||||
| 						temp_cnt := 0; | ||||
| 						if status_update_stb = '1' then | ||||
| 							state <= GETSTATUS; | ||||
| 						end if; | ||||
| 						if load_stb = '1' then --debug only | ||||
| 							state <= GETINFO; | ||||
| 						end if; | ||||
| 					when GETSTATUS => | ||||
| 						run_command_single(8, 8, 16, 3, FLASHROM_COMMAND_GET_STATUS & padBits(spif_data_in, FLASHROM_COMMAND_GET_STATUS)); | ||||
| 						if done then | ||||
| 							status <= spif_data_out(7 downto 0); | ||||
| 						if temp_cnt = 5 then | ||||
| 							spif_data_in_valid <= '0'; | ||||
| 						elsif spif_data_next = '1' then | ||||
| 							temp_cnt := temp_cnt + 1; | ||||
| 						end if; | ||||
| 					when IDLE => null; | ||||
| 				end case; | ||||
| 			end if; | ||||
| 		end if; | ||||
| 	end process flashrom_controller_p; | ||||
| 	ready <= '1' when state = IDLE else '0'; | ||||
| end architecture RTL; | ||||
|  | ||||
| @ -5,7 +5,6 @@ use ieee.numeric_std.all; | ||||
| package flashrom_pkg is | ||||
| 	constant FLASHROM_ADDR_WIDTH              : integer                      := 12; | ||||
| 	constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F"; | ||||
| 	constant FLASHROM_COMMAND_GET_STATUS      : std_logic_vector(7 downto 0) := x"D7"; | ||||
| 
 | ||||
| 	function padBits(target : std_logic_vector; other : std_logic_vector) return std_logic_vector; | ||||
| end package flashrom_pkg; | ||||
|  | ||||
| @ -92,15 +92,9 @@ begin | ||||
| 						ckDiv <= 0; | ||||
| 					when TX => | ||||
| 						if ckDiv = clk_divider - 2 or pseudoEdge then | ||||
| 							ckDiv <= 0; | ||||
| 							if not pseudoEdge then | ||||
| 								spi_sck <= not spi_sck; | ||||
| 							end if; | ||||
| 							if spi_sck = '0' and bitCounter = data_in_length_i and data_in_valid = '0' then | ||||
| 								-- Prevent last clock cycle (make it a "passive" one) | ||||
| 								spi_sck    <= '0'; | ||||
| 								pseudoEdge <= true; | ||||
| 							end if; | ||||
| 							if spi_sck = '1' or pseudoEdge then -- falling edge -> provide data | ||||
| 								if bitCounter = data_in_length_i then | ||||
| 									bitCounter <= 0; | ||||
|  | ||||
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