fpga/mor1kx-bemicrocv
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compare: fpga:3fffa6efe3769d70fdc99fd7046a0eb243e80957
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1 changed files with 18 additions and 18 deletions
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36
design/top.vhd
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@ -59,12 +59,12 @@ architecture RTL of top is
-- WB config -- WB config
constant masters : natural := 3; constant masters : natural := 3;
constant slaves : natural := 4; constant slaves : natural := 5;
--constant INTERCON_ID_SRAM : natural := 0; constant INTERCON_ID_SRAM : natural := 0;
constant INTERCON_ID_DDR3 : natural := 0; constant INTERCON_ID_DDR3 : natural := 1;
constant INTERCON_ID_FLASH : natural := 1; constant INTERCON_ID_FLASH : natural := 2;
constant INTERCON_ID_GPIO : natural := 2; constant INTERCON_ID_GPIO : natural := 3;
constant INTERCON_ID_UART : natural := 3; constant INTERCON_ID_UART : natural := 4;
-- constant INTERCON_ID_NS16550 : natural := 4; -- constant INTERCON_ID_NS16550 : natural := 4;
constant in_simulation : boolean := false constant in_simulation : boolean := false
@ -144,13 +144,13 @@ begin
pll_locked <= '1'; pll_locked <= '1';
-- SRAM -- SRAM
-- sram_wb_inst : entity work.sram_wb sram_wb_inst : entity work.sram_wb
-- port map( port map(
-- clk => clk, clk => clk,
-- rst => rst, rst => rst,
-- wb_in => intercon_slave_i(INTERCON_ID_SRAM), wb_in => intercon_slave_i(INTERCON_ID_SRAM),
-- wb_out => intercon_slave_o(INTERCON_ID_SRAM) wb_out => intercon_slave_o(INTERCON_ID_SRAM)
-- ); );
-- CPU -- CPU
interrupt <= (others => '0'); interrupt <= (others => '0');
@ -298,7 +298,7 @@ begin
if rst = '1' then if rst = '1' then
avl_reqEn <= '1'; avl_reqEn <= '1';
elsif rising_edge(clk) then elsif rising_edge(clk) then
if intercon_slave_i(INTERCON_ID_DDR3).STB = '1' and not intercon_slave_o(INTERCON_ID_DDR3).ACK= '1' then if intercon_slave_i(INTERCON_ID_DDR3).STB = '1' then
avl_reqEn <= '0'; avl_reqEn <= '0';
else else
avl_reqEn <= '1'; avl_reqEn <= '1';
@ -363,16 +363,16 @@ begin
master_i => intercon_slave_o, master_i => intercon_slave_o,
master_o => intercon_slave_i, master_o => intercon_slave_i,
address => ( address => (
--INTERCON_ID_SRAM => x"00000000", INTERCON_ID_SRAM => x"00000000",
INTERCON_ID_DDR3 => x"00000000", INTERCON_ID_DDR3 => x"10000000",
INTERCON_ID_FLASH => x"40000000", INTERCON_ID_FLASH => x"40000000",
INTERCON_ID_GPIO => x"80000000", INTERCON_ID_GPIO => x"80000000",
INTERCON_ID_UART => x"80000100" INTERCON_ID_UART => x"80000100"
), ),
mask => ( mask => (
--INTERCON_ID_SRAM => x"ffffff00", -- TODO: Match size of SRAM (or remove) INTERCON_ID_SRAM => x"ffff0000",
INTERCON_ID_DDR3 => x"f0000000", INTERCON_ID_DDR3 => x"f0000000",
INTERCON_ID_FLASH => x"fffff000", -- TODO: Correct size INTERCON_ID_FLASH => x"f0000000",
INTERCON_ID_GPIO => x"fffffff0", INTERCON_ID_GPIO => x"fffffff0",
INTERCON_ID_UART => x"ffffffc0" INTERCON_ID_UART => x"ffffffc0"
) )