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@ -59,12 +59,12 @@ architecture RTL of top is
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-- WB config
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constant masters : natural := 3;
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constant slaves : natural := 4;
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--constant INTERCON_ID_SRAM : natural := 0;
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constant INTERCON_ID_DDR3 : natural := 0;
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constant INTERCON_ID_FLASH : natural := 1;
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constant INTERCON_ID_GPIO : natural := 2;
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constant INTERCON_ID_UART : natural := 3;
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constant slaves : natural := 5;
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constant INTERCON_ID_SRAM : natural := 0;
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constant INTERCON_ID_DDR3 : natural := 1;
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constant INTERCON_ID_FLASH : natural := 2;
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constant INTERCON_ID_GPIO : natural := 3;
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constant INTERCON_ID_UART : natural := 4;
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-- constant INTERCON_ID_NS16550 : natural := 4;
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constant in_simulation : boolean := false
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@ -144,13 +144,13 @@ begin
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pll_locked <= '1';
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-- SRAM
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-- sram_wb_inst : entity work.sram_wb
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-- port map(
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-- clk => clk,
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-- rst => rst,
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-- wb_in => intercon_slave_i(INTERCON_ID_SRAM),
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-- wb_out => intercon_slave_o(INTERCON_ID_SRAM)
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-- );
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sram_wb_inst : entity work.sram_wb
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port map(
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clk => clk,
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rst => rst,
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wb_in => intercon_slave_i(INTERCON_ID_SRAM),
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wb_out => intercon_slave_o(INTERCON_ID_SRAM)
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);
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-- CPU
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interrupt <= (others => '0');
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@ -298,7 +298,7 @@ begin
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if rst = '1' then
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avl_reqEn <= '1';
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elsif rising_edge(clk) then
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if intercon_slave_i(INTERCON_ID_DDR3).STB = '1' and not intercon_slave_o(INTERCON_ID_DDR3).ACK= '1' then
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if intercon_slave_i(INTERCON_ID_DDR3).STB = '1' then
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avl_reqEn <= '0';
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else
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avl_reqEn <= '1';
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@ -363,16 +363,16 @@ begin
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master_i => intercon_slave_o,
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master_o => intercon_slave_i,
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address => (
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--INTERCON_ID_SRAM => x"00000000",
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INTERCON_ID_DDR3 => x"00000000",
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INTERCON_ID_SRAM => x"00000000",
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INTERCON_ID_DDR3 => x"10000000",
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INTERCON_ID_FLASH => x"40000000",
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INTERCON_ID_GPIO => x"80000000",
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INTERCON_ID_UART => x"80000100"
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),
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mask => (
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--INTERCON_ID_SRAM => x"ffffff00", -- TODO: Match size of SRAM (or remove)
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INTERCON_ID_SRAM => x"ffff0000",
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INTERCON_ID_DDR3 => x"f0000000",
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INTERCON_ID_FLASH => x"fffff000", -- TODO: Correct size
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INTERCON_ID_FLASH => x"f0000000",
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INTERCON_ID_GPIO => x"fffffff0",
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INTERCON_ID_UART => x"ffffffc0"
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)
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