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e053da3ae1
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054ae0e210
@ -33,7 +33,7 @@ architecture rtl of bench_flashrom_controller is
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end procedure strobe;
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end procedure strobe;
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signal clr : std_logic;
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signal clr : std_logic;
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signal ready : std_logic;
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signal ready : std_logic;
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signal page : std_logic_vector(FLASHROM_PAGE_ADDR_WIDTH - 1 downto 0);
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signal page : std_logic_vector(FLASHROM_ADDR_WIDTH - 1 downto 0);
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signal sync_stb : std_logic;
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signal sync_stb : std_logic;
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signal load_stb : std_logic;
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signal load_stb : std_logic;
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signal status_update_stb : std_logic;
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signal status_update_stb : std_logic;
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@ -1,173 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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library ip;
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use ip.wishbone_package.all;
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entity bench_flashrom_wb is
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end entity bench_flashrom_wb;
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architecture RTL of bench_flashrom_wb is
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signal clk : std_logic;
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signal rst : std_logic;
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signal clr : std_logic;
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signal wb_in : wishbone_v3_slave_in;
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signal wb_out : wishbone_v3_slave_out;
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signal spi_si : std_logic;
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signal spi_so : std_logic;
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signal spi_sck : std_logic;
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signal spi_reset_n : std_logic;
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signal spi_cs_n : std_logic;
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signal spi_wp_n : std_logic;
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signal spi_busy : std_logic;
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procedure waitclk is
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begin
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wait until rising_edge(clk);
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end procedure waitclk;
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procedure waitnclk(n : integer) is
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begin
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for i in 1 to n loop
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wait until rising_edge(clk);
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end loop;
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end procedure waitnclk;
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procedure strobe(signal s : out std_logic) is
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begin
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s <= '1';
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waitclk;
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s <= '0';
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waitclk;
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end procedure strobe;
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begin
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DataFlash_inst : entity work.DataFlash
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generic map(
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flashmemory => "devicemodels/memory.txt",
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Rapid_interface => true,
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fsck => 66,
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DEVICE => "AT45DB011D", --AT45DB011D
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Tsck => 13.6 ns)
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port map(
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SI => spi_si,
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CSB => spi_cs_n,
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SCK => spi_sck,
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WPB => spi_wp_n,
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RESETB => spi_reset_n,
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SO => spi_so,
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RDYBSY => spi_busy
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);
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flashrom_wb_inst : entity design.flashrom_wb
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port map(
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clk => clk,
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rst => rst,
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clr => clr,
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wb_in => wb_in,
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wb_out => wb_out,
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spi_si => spi_si,
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spi_so => spi_so,
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spi_sck => spi_sck,
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spi_reset_n => spi_reset_n,
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spi_cs_n => spi_cs_n,
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spi_wp_n => spi_wp_n
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);
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clock_driver : process
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constant period : time := 10 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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test : process is
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begin
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rst <= '1';
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wb_in.ADR <= (others => '0');
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wait for 10 ns * 2;
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wait until (rising_edge(clk));
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rst <= '0';
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wait for 10 ns * 2;
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wait until (rising_edge(clk));
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wb_in.ADR <= std_logic_vector(to_unsigned(0, 32));
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wb_in.CYC <= '1';
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wb_in.STB <= '1';
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wb_in.WE <= '0';
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wait until wb_out.ACK = '1';
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wb_in.CYC <= '0';
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wb_in.STB <= '0';
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waitnclk(30);
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wb_in.ADR <= std_logic_vector(to_unsigned(4, 32));
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wb_in.CYC <= '1';
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wb_in.STB <= '1';
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wb_in.WE <= '0';
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wait until wb_out.ACK = '1';
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wb_in.CYC <= '0';
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wb_in.STB <= '0';
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waitnclk(30);
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wb_in.ADR <= std_logic_vector(to_unsigned(4, 32));
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wb_in.DAT <= x"deadbeef";
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wb_in.CYC <= '1';
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wb_in.STB <= '1';
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wb_in.WE <= '1';
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wait until wb_out.ACK = '1';
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wb_in.CYC <= '0';
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wb_in.STB <= '0';
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waitnclk(30);
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wb_in.ADR <= std_logic_vector(to_unsigned(4, 32));
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wb_in.CYC <= '1';
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wb_in.STB <= '1';
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wb_in.WE <= '0';
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wait until wb_out.ACK = '1';
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wb_in.CYC <= '0';
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wb_in.STB <= '0';
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waitnclk(30);
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wb_in.ADR <= std_logic_vector(to_unsigned(256, 32));
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wb_in.CYC <= '1';
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wb_in.STB <= '1';
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wb_in.WE <= '0';
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wait until wb_out.ACK = '1';
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wb_in.CYC <= '0';
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wb_in.STB <= '0';
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waitnclk(30);
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wb_in.ADR <= std_logic_vector(to_unsigned(256, 32));
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wb_in.DAT <= x"b000b1e5";
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wb_in.CYC <= '1';
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wb_in.STB <= '1';
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wb_in.WE <= '1';
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wait until wb_out.ACK = '1';
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wb_in.CYC <= '0';
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wb_in.STB <= '0';
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waitnclk(30);
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wb_in.ADR <= std_logic_vector(to_unsigned(256, 32));
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wb_in.CYC <= '1';
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wb_in.STB <= '1';
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wb_in.WE <= '0';
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wait until wb_out.ACK = '1';
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wb_in.CYC <= '0';
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wb_in.STB <= '0';
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waitnclk(30);
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wb_in.ADR <= std_logic_vector(to_unsigned(4, 32));
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wb_in.CYC <= '1';
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wb_in.STB <= '1';
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wb_in.WE <= '0';
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wait until wb_out.ACK = '1';
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wb_in.CYC <= '0';
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wb_in.STB <= '0';
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waitnclk(30);
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wait;
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end process test;
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end architecture RTL;
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@ -12,7 +12,7 @@ entity flashrom_controller is
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-- Control IF
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-- Control IF
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ready : out std_logic; -- The controller is ready to accept commands
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ready : out std_logic; -- The controller is ready to accept commands
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page : in std_logic_vector(FLASHROM_PAGE_ADDR_WIDTH - 1 downto 0);
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page : in std_logic_vector(FLASHROM_ADDR_WIDTH - 1 downto 0);
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sync_stb : in std_logic; -- Synchronize current memory page with chip, only sampled when ready
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sync_stb : in std_logic; -- Synchronize current memory page with chip, only sampled when ready
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load_stb : in std_logic; -- Load page into local buffer, only sampled when ready
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load_stb : in std_logic; -- Load page into local buffer, only sampled when ready
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status_update_stb : in std_logic; -- Update status vector
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status_update_stb : in std_logic; -- Update status vector
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@ -28,7 +28,7 @@ entity flashrom_controller is
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-- SPI flash hardware signals
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-- SPI flash hardware signals
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spi_si : out std_logic; -- SPI serial in
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spi_si : out std_logic; -- SPI serial in
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spi_so : in std_logic; -- SPI serial out
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spi_so : in std_logic; -- SPI serial out
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spi_sck : out std_logic; -- SPI clock
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spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module
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spi_reset_n : out std_logic; -- SPI hard reset
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spi_reset_n : out std_logic; -- SPI hard reset
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spi_cs_n : out std_logic; -- SPI chip select
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spi_cs_n : out std_logic; -- SPI chip select
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spi_wp_n : out std_logic -- SPI write protect
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spi_wp_n : out std_logic -- SPI write protect
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@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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package flashrom_pkg is
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package flashrom_pkg is
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constant FLASHROM_PAGE_ADDR_WIDTH : integer := 12;
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constant FLASHROM_ADDR_WIDTH : integer := 12;
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constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F";
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constant FLASHROM_COMMAND_MANUFACTURER_ID : std_logic_vector(7 downto 0) := x"9F";
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constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7";
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constant FLASHROM_COMMAND_GET_STATUS : std_logic_vector(7 downto 0) := x"D7";
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constant FLASHROM_COMMAND_CONT_ARRAY_READ : std_logic_vector(7 downto 0) := x"0B";
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constant FLASHROM_COMMAND_CONT_ARRAY_READ : std_logic_vector(7 downto 0) := x"0B";
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@ -16,7 +16,7 @@ entity flashrom_spi is
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-- SPI flash hardware signals
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-- SPI flash hardware signals
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spi_si : out std_logic; -- SPI serial in
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spi_si : out std_logic; -- SPI serial in
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spi_so : in std_logic; -- SPI serial out
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spi_so : in std_logic; -- SPI serial out
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spi_sck : out std_logic; -- SPI clock
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spi_sck : out std_logic; -- Create clock using PLL, then supply to chip and this module
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spi_cs_n : out std_logic; -- SPI chip select
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spi_cs_n : out std_logic; -- SPI chip select
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-- Logic interface
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-- Logic interface
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@ -1,202 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library ip;
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use ip.wishbone_package.all;
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use ip.all;
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use work.flashrom_pkg.all;
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entity flashrom_wb is
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port(
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clk : in std_logic;
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rst : in std_logic;
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clr : in std_logic;
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-- Wishbone
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wb_in : in wishbone_v3_slave_in;
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wb_out : out wishbone_v3_slave_out;
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-- SPI Flash Hardware Signals
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spi_si : out std_logic; -- spi serial in
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spi_so : in std_logic; -- spi serial out
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spi_sck : out std_logic; -- spi clock
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spi_reset_n : out std_logic; -- spi hard reset
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spi_cs_n : out std_logic; -- spi chip select
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spi_wp_n : out std_logic -- spi write protect
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);
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end entity flashrom_wb;
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architecture rtl of flashrom_wb is
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-- Controller Signals
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signal current_page : std_logic_vector(FLASHROM_PAGE_ADDR_WIDTH - 1 downto 0);
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signal ready : std_logic;
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signal sync_stb : std_logic;
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signal load_stb : std_logic;
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signal status_update_stb : std_logic;
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signal status : std_logic_vector(7 downto 0);
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signal info : std_logic_vector(31 downto 0);
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signal data_in : std_logic_vector(7 downto 0);
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signal data_in_next : std_logic;
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signal data_out : std_logic_vector(7 downto 0);
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signal data_out_valid : std_logic;
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--
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signal bootup_complete : std_logic;
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type state_t is (WAITCON, IDLE, LOADPAGE, WRITEPAGE);
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signal state : state_t;
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--
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signal requested_page : std_logic_vector(current_page'range);
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signal requested_byte : std_logic_vector(7 downto 0);
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signal dirty : std_logic;
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-- Cache Memory
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type cache_t is array (0 to 63) of std_logic_vector(31 downto 0);
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signal cache : cache_t;
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signal cache_addr : std_logic_vector(7 downto 0);
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signal cache_control_addr : unsigned(7 downto 0);
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signal cache_we : std_logic;
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signal cache_dOut : std_logic_vector(31 downto 0);
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signal cache_dIn : std_logic_vector(31 downto 0);
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signal data_in_shift : std_logic_vector(31 downto 0);
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signal delay_cycle : std_logic;
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begin
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flashrom_controller_inst : entity work.flashrom_controller
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port map(
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clk => clk,
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rst => rst,
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clr => clr,
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page => current_page,
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ready => ready,
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sync_stb => sync_stb,
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load_stb => load_stb,
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status_update_stb => status_update_stb,
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status => status,
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info => info,
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data_in => data_in,
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data_in_next => data_in_next,
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data_out => data_out,
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data_out_valid => data_out_valid,
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spi_si => spi_si,
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spi_so => spi_so,
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spi_sck => spi_sck,
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spi_reset_n => spi_reset_n,
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spi_cs_n => spi_cs_n,
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spi_wp_n => spi_wp_n
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);
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wb_ctrl : process(clk, rst) is
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procedure default_state is
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begin
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load_stb <= '0';
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sync_stb <= '0';
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wb_out.ACK <= '0';
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cache_we <= '0';
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delay_cycle <= '0';
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end procedure default_state;
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procedure reset_state is
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begin
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default_state;
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state <= WAITCON;
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bootup_complete <= '0';
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dirty <= '0';
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end procedure reset_state;
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begin
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if rst = '1' then
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reset_state;
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elsif rising_edge(clk) then
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default_state;
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if clr = '1' then
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reset_state;
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else
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case state is
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when WAITCON =>
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if ready = '1' then
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state <= IDLE;
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end if;
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when IDLE =>
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if ready = '1' and delay_cycle = '0' then
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if wb_in.CYC = '1' and wb_in.STB = '1' then
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if (requested_page /= current_page) then -- Page swap required
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if (dirty = '0') then
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state <= LOADPAGE;
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load_stb <= '1';
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cache_control_addr <= (others => '1'); -- Wraparound...
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end if;
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if (dirty = '1') then
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state <= WRITEPAGE;
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sync_stb <= '1';
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cache_control_addr <= to_unsigned(1, cache_control_addr'length);
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end if;
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else -- Same page
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wb_out.ACK <= '1';
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|
||||||
if wb_in.WE = '1' then
|
|
||||||
dirty <= '1';
|
|
||||||
cache_dIn <= wb_in.DAT;
|
|
||||||
cache_we <= '1';
|
|
||||||
cache_control_addr <= unsigned(wb_in.ADR(7 downto 0));
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
if (bootup_complete = '0') then
|
|
||||||
state <= LOADPAGE;
|
|
||||||
load_stb <= '1';
|
|
||||||
cache_control_addr <= (others => '1'); -- Wraparound...
|
|
||||||
end if;
|
|
||||||
when LOADPAGE =>
|
|
||||||
bootup_complete <= '1';
|
|
||||||
current_page <= requested_page;
|
|
||||||
if data_out_valid = '1' then
|
|
||||||
cache_dIn <= cache_dIn(23 downto 0) & data_out;
|
|
||||||
cache_control_addr <= cache_control_addr + 1;
|
|
||||||
cache_we <= '1';
|
|
||||||
if cache_control_addr = 254 then
|
|
||||||
state <= IDLE;
|
|
||||||
delay_cycle <= '1';
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
when WRITEPAGE =>
|
|
||||||
if cache_control_addr = 1 then
|
|
||||||
data_in_shift <= cache_dOut;
|
|
||||||
end if;
|
|
||||||
if data_in_next = '1' then
|
|
||||||
if cache_control_addr(1 downto 0) = "00" then
|
|
||||||
data_in_shift <= cache_dOut;
|
|
||||||
else
|
|
||||||
data_in_shift <= data_in_shift(23 downto 0) & x"00";
|
|
||||||
end if;
|
|
||||||
cache_control_addr <= cache_control_addr + 1;
|
|
||||||
|
|
||||||
if cache_control_addr = 0 then
|
|
||||||
state <= IDLE;
|
|
||||||
dirty <= '0';
|
|
||||||
delay_cycle <= '1';
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end case;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process wb_ctrl;
|
|
||||||
requested_page <= wb_in.ADR(FLASHROM_PAGE_ADDR_WIDTH + 8 - 1 downto 8);
|
|
||||||
requested_byte <= wb_in.ADR(7 downto 0);
|
|
||||||
data_in <= data_in_shift(31 downto 24);
|
|
||||||
|
|
||||||
-- Cache Memory Controller
|
|
||||||
cache_mem_p : process(clk, rst) is
|
|
||||||
begin
|
|
||||||
if rst = '1' then
|
|
||||||
cache_dOut <= (others => '0');
|
|
||||||
elsif rising_edge(clk) then
|
|
||||||
cache_dOut <= cache(to_integer(unsigned(cache_addr(cache_addr'length - 1 downto 2))));
|
|
||||||
if cache_we = '1' then
|
|
||||||
cache(to_integer(unsigned(cache_addr(cache_addr'length - 1 downto 2)))) <= cache_dIn;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process cache_mem_p;
|
|
||||||
|
|
||||||
cache_addr <= wb_in.ADR(7 downto 0) when (state = IDLE and cache_we = '0') else std_logic_vector(cache_control_addr);
|
|
||||||
wb_out.DAT <= cache_dOut;
|
|
||||||
end architecture rtl;
|
|
||||||
@ -1,89 +0,0 @@
|
|||||||
onerror {resume}
|
|
||||||
quietly WaveActivateNextPane {} 0
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/clk
|
|
||||||
add wave -noupdate /bench_flashrom_wb/DataFlash_inst/RDYBSY
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/rst
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/clr
|
|
||||||
add wave -noupdate -expand /bench_flashrom_wb/flashrom_wb_inst/wb_in
|
|
||||||
add wave -noupdate -expand /bench_flashrom_wb/flashrom_wb_inst/wb_out
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/spi_si
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/spi_so
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/spi_sck
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/spi_reset_n
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/spi_cs_n
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/spi_wp_n
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/current_page
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/ready
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/sync_stb
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/load_stb
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/status_update_stb
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/status
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/info
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/data_in
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/data_in_next
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/data_out
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/data_out_valid
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/bootup_complete
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/state
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/requested_page
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/requested_byte
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/dirty
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/cache_we
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/cache_addr
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/cache_control_addr
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/cache_dOut
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/cache_dIn
|
|
||||||
add wave -noupdate /bench_flashrom_wb/flashrom_wb_inst/cache
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/rst
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/clr
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/ready
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/page
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/sync_stb
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/load_stb
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/status_update_stb
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/status
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/info
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/data_in
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/data_in_next
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/data_out
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/data_out_valid
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spi_si
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spi_so
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spi_sck
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spi_reset_n
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spi_cs_n
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spi_wp_n
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/state
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_data_in_valid
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_data_in
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_data_in_length
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_data_next
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_data_out
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_data_out_valid
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_data_out_length
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/words_sent
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_data_out_dummy_bits
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_transmission_active
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/command_is_latched
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/spif_max_word_length
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/max_dummy_bits
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/bootup_delay
|
|
||||||
add wave -noupdate -expand -group flashrom-ctrlr /bench_flashrom_wb/flashrom_wb_inst/flashrom_controller_inst/status_reg_poll_delay
|
|
||||||
TreeUpdate [SetDefaultTree]
|
|
||||||
WaveRestoreCursors {{Cursor 1} {182209 ns} 0}
|
|
||||||
quietly wave cursor active 1
|
|
||||||
configure wave -namecolwidth 173
|
|
||||||
configure wave -valuecolwidth 100
|
|
||||||
configure wave -justifyvalue left
|
|
||||||
configure wave -signalnamewidth 1
|
|
||||||
configure wave -snapdistance 10
|
|
||||||
configure wave -datasetprefix 0
|
|
||||||
configure wave -rowmargin 4
|
|
||||||
configure wave -childrowmargin 2
|
|
||||||
configure wave -gridoffset 0
|
|
||||||
configure wave -gridperiod 1
|
|
||||||
configure wave -griddelta 40
|
|
||||||
configure wave -timeline 0
|
|
||||||
configure wave -timelineunits ns
|
|
||||||
update
|
|
||||||
WaveRestoreZoom {168208 ns} {199740 ns}
|
|
||||||
Loading…
Reference in New Issue
Block a user